Features and Benefits
- 4 Differential transmitters
- 4 Differential receivers
- 2 observation receivers with 2 inputs each
- Center frequency: 75 MHz to 6000 MHz
- Fully integrated DPD adaptation engine for power amplifier linearization
- Crest factor reduction engine
- Maximum receiver bandwidth: 200 MHz
- Maximum transmitter large signal bandwidth: 200 MHz
- Maximum transmitter synthesis bandwidth: 450 MHz
- Maximum observation receiver bandwidth: 450 MHz
- Fully integrated independent fractional-N radio frequency synthesizers
- Fully integrated clock synthesizer
- Multichip phase synchronization for all local oscillators and baseband clocks
- Support for TDD and FDD applications
- 24.33 Gbps JESD204B/JESD204C digital interface
The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.
The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.
The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.
To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.
A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.
This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.
The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.
The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.
The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm × 14 mm, 289-ball chip scale ball grid array (CSP_BGA).
- 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations
Markets & Technology
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
The ADRV9029 and ADRV9026 radio cards designed to showcase the ADRV9026 (quad-channel wideband RF transceiver) and ADRV9029 (quad-channel wideband RF transceiver with integrated DPD & CFR). The radio cards provide a 4x4 transceiver platform for device evaluation. All peripherals necessary for the radio card to operate include a separate high efficiency power circuit board, and a high-performance clocking solution included on the radio board. Connecting one of the radio cards with the FPGA motherboard ADS9-V2EBZ through the FMC connector form a complete evaluation platform for ADRV9026 and ADRV9029. The ADRV9026 evaluation kit can also be used to evaluate the performance of the ADRV9010.
Features & Benefits
- Complete ADRV9026 radio cards for evaluation
- ADRV9026-HB/PCBZ for frequency band 2.8GHz to 6GHz
- ADRV9026-MB/PCBZ for frequency band 650MHz to 2.8GHz
- ADRV9026-LB/PCBZ for frequency band 75MHz to 1000MHz
- Complete ADRV9029 radio cards for evaluation
- ADRV9029-HB/PCBZ (integrated DPD & CFR) for frequency band 2.8GHz to 6GHz
- ADRV9029-MB/PCBZ (integrated DPD & CFR) for frequency band 650MHz to 2.8GHz
- 4x4 Wideband RF transceiver platform operating over 650MHz to 6GHz frequency range
- A separate power daughter card provides reference design for high efficiency power supply solution
- FMC connector to FPGA motherboard ADS9-V2EBZ
- Includes schematics, layout, BOM, API and evaluation software
When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Features & Benefits
Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.
- One (1) FMC+ connector.
- Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
- HMC DRAM
- Simple USB 3.0 port interface.
- Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE™ evaluation boards.
Software & Systems Requirements
ADRV9029 Released Software SW188.8.131.52
ADRV9026/ADRV9029 - SDCARD
ADRV9029 Release Build Software Release Notes SW184.108.40.206
Tools & Simulations
The Design File Package includes the eval board schematics, BOM, layout, IBIS, BSDL models, JCOM models, S-parameters Material Declaration, and Symbols and Footprints.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.