Design & Integration Files
- Bill of Materials
- Gerber Files
- PADS Files
- Assembly Drawing
Part Numbers with "Z" indicate RoHS Compliance. Boards checked are needed to evaluate this circuit.
- EVAL-CN0372-PMDZ ($55.00) Ultralow Power, Multichannel Data Acquisition System with Energy Harvesting Circuit
- EVAL-SDP-CB1Z ($108.90) Eval Control Board
- SDP-PMD-IB1Z ($60.50) PMOD to SDP Interposer Board
Software such as C code and/or FPGA code, used to communicate with component's digital interface.
Features & Benefits
- Ultralow Power Data Acquisition System
- 4-Channels, 12-Bit Resolution
- Energy Harvesting Power Circuit
Markets and Technologies
Circuit Function & Benefits
The circuit shown in Figure 1 is an ultralow power, multichannel data acquisition system that can be powered by a photovoltaic (PV) cell or thermoelectric generator (TEG). The circuit uses the industry’s lowest power, multichannel, 12-bit successive approximation analog-to-digital converter (SAR ADC), the AD7091R-5, along with an efficient energy harvesting circuit based on the ADP5090 boost regulator. The ADC has a typical power consumption of 100 μW on a single 3 V supply when sampling at 22 kSPS. Typical signal-to-noise ratio (SNR) is 68 dB for a 1 kHz input signal.
The low power consumption and small form factor make this combination of devices ideally suited for portable low power applications, particularly for wearable and self-powered devices.
This circuit provides an optimized low power compact solution for multichannel system monitoring. These characteristics are particularly important in wearable and self-powered applications where form factor and power consumption are critical system specifications.
The AD7091R-5 is a 12-bit, ultralow power, successive approximation ADC. The device operates from a single 2.7 V to 5.25 V power supply. This ADC features an on-chip conversion clock, an accurate reference, and an I2C interface that operates in both standard (fSCL = 100 kHz) and fast (fSCL = 400 kHz) modes.
The conversion process and data acquisition are controlled using the I2C interface and an internal oscillator. The AD7091R-5 interface allows data read after the conversion, achieving a maximum 22.22 kSPS throughput rate in fast mode. This device uses advanced design and process techniques to achieve ultralow power dissipation without compromising performance. An on-chip, accurate 2.5 V reference is available on the REFIN/REFOUT pin.
The AD7091R-5 has an autocycle mode that allows the user to configure the ADC for autonomous operation and is ideal for the monitoring of events outside of a user defined range. Conversions automatically take place at configured intervals as shown in Table 25 of the AD7091R-5 data sheet. Typically, this mode is used to monitor a selection of channels with limit registers programmed to signal out of bounds conditions via the alert function.
The ADP5090 is an integrated boost regulator that converts dc power from photovoltaic cells or thermoelectric generators. The device charges storage elements (rechargeable battery or super capacitor). The CN-0372 board uses a super capacitor that supplies power for small electronic devices and battery-free systems. The ADP5090 provides efficient conversion of the small amounts of harvested power available from PV cells or TEGs. The ADP5090 operates on an input power range from 16 μW to 200 mW range with sub-microwatt operation losses.
With the internal cold-start circuit, the regulator can start operating at an input voltage as low as 380 mV. This solution eliminates the need for an external battery to power the circuit (although backup battery options are available) and makes full use of harvestable energy instead.
The SYS voltage output of the ADP5090 supplies the entire circuit as shown in Figure 1.
The circuit in Figure 2 shows the minimal connections needed for the AD7091R-5 ADC.
The analog input range for the AD7091R-5 is 0 V to VREF and is unipolar. The circuit is not designed to accept negative voltages. While the AD7091R-5 contains a wide bandwidth track-and-hold amplifier that can handle input frequencies up to 1.5 MHz, the circuit is tested to resolve lower frequencies up to 2 kHz in fast mode.
The AD7091R-5 provides access to the multiplexer output eliminating the need for a signal conditioning circuit in each channel when additional filtering is required. The input signal of the active channel appears at MUXOUT. The filters before the ADC VIN pins are designed to have a cutoff frequency of about 8.6 MHz. These filters attenuate noise at the ADC input and absorb the charge kickbacks from the ADC. It is recommended to use a low series resistance value and a reasonably sized capacitor that can source and sink the high frequency charge kickbacks from the ADC.
If no additional filtering or signal conditioning is required, the MUXOUT pin is tied directly to ADCIN. Control of the AD7091R-5 is through the I2C-compatible serial bus.
Figure 3 shows the ADP5090 energy harvesting circuit. The circuit converts power from an energy source connected to the J4 terminal, stores charge in the super capacitor (C26), and provides power to the entire circuit.
Harvested energy from a PV cell or TEG is introduced at ENERGY_IN. When ENERGY_IN exceeds 380 mV, the ADP5090 enters cold start-up. The device then exits cold-startup, and main boost is enabled when the SYS voltage exceeds VSYS_TH, which is typically 1.93 V. The logic high level on PGOOD is equal to the SYS voltage, and when the battery terminal voltage is reached, the main boost charger is turned off.
The ADP5090 boost regulator operates in pulse frequency mode (PFM), transferring energy stored in the input capacitor to SYS and the C26 super capacitor (Cellergy CLG03P050F17, 50 mF, 3.5 V). A PGOOD threshold is set by external connectors to indicate that the SYS voltage is at an acceptable voltage, given by
RPG1 and RPG2 are the values from Figure 3.
VREF_ADP5090 is typically 1.21 V.
The ADP5090 is also equipped with battery overcharging and discharging protection thresholds, which are also set by external resistors.
To prevent overcharging, the rising threshold for the battery terminal voltage is given by
where RTERM1 and RTERM2 are the values from Figure 3.
To prevent deep discharge, the falling threshold for the battery discharge shutdown voltage is given by
where RSD1 and RSD2 are the values from Figure 3.
An illustration of these threshold voltages is shown in Figure 4.
The circuit in Figure 3 also has a provision through SL7 to provide a low energy state backup option to accelerate cold-start.
A complete documentation package including schematics, board layout, and bill of materials (BOM) can be found at www.analog.com/CN0372-DesignSupport. The circuit is compatible with the Digilent PMOD interface standard.
Measurement Results for DAS with Energy Harvesting Circuit
The circuit comes with a graphical user interface that facilitates configuring the devices on-board and evaluating the circuit performance. Tabs are available for device configuration, as well as for displaying noise performance, histogram, and register readout. For a complete description of the software package, see the CN-0372 Software User Guide.
Figure 5 and Figure 6 show the ac performance of the circuit, configured with MUXOUT connected directly to ADCIN, for a 2.4 V p-p, 1 kHz sine wave with a common-mode voltage of 1.25 V. While the default configuration generates a 3.3 V supply on SYS, all measurements in this circuit note were taken with the external resistors configured for 3 V supplies.
Power consumed is computed using the following equation:
The circuit, configured without the buffer and with VDD and VDRIVE coming from SYS, consumes 34 μA.
An on-board option for external buffering of the MUXOUT signal using an ADA4805-1 is available, as well as an option to use the backup battery to power an on-board ADP1607 regulator to generate the board supply rails.
Figure 7 shows the on-board optional buffer circuitry. When used, R6 is removed, SL9 and SL12 are set to Position B, SL13 is set to Position A, and R43 is installed. The circuit also has provisions for any gain, attenuation, or level shifting that is desired. The ADA4805-1 consumes approximately 500 μA of quiescent current, but has the option to power down and scale with throughput. As shown in Figure 8, controlling the ADA4805-1 SHUTDOWN pin allows users to dynamically manage its power consumption. Adjusting the duty cycle of the SHUTDOWN signal through the evaluation software achieves significant power savings.
See the CN-0372 Software User Guide for additional details on controlling the power-scaling feature of the ADA4805-1 in the evaluation software.
With power scaling, the equation for consumed power becomes
PT is the total consumed power.
IQ is the quiescent current.
tAMP, ON is the time the ADA4805-1 is on.
tS is the sampling time.
Overall system consumption with the ADA4805-1 in use and dynamically powered, and with VDD and VDRIVE coming from SYS, was as low as 70 μA without performance degradation, as shown in Figure 9.
Table 1 shows typical current consumption of the circuit at different configurations.
|Without Buffer Amplifier||34|
|AD7091R-5 in Full Power Down||13.4|
| AD7091R-5 in Full Power Down,
No Internal Reference
|With Buffer Amplifier Always On||530|
|AD7091R-5 in Full Power Down||520.4|
| AD7091R-5 in Full Power Down,
No Internal Reference
|Dynamic Power Scaling with Buffer Amplifier||See Figure 9|
Typical performance and current consumption of the system with different duty cycles is shown in Figure 9.
Figure 10 shows the optional ADP1607 circuitry, which can be configured through SL7 to be powered by the B3 backup battery in Figure 3.
The output voltage is configured by the R28 and R29 external resistors for a 3 V output using the following equation:
VFB = 1.259 V.
IFB = 0.1 μA.
Circuit Evaluation & Test
This circuit uses the EVAL-CN0372-PMDZ circuit board, the SDP-PMD-IB1Z interposer board, and the EVAL-SDP-CB1Z system demonstration platform (SDP) board. The PMOD interposer board and the SDP controller board have 120-pin mating connectors. The interposer board and the EVAL-CN0372-PMDZ board have 12-pin PMOD interface Type 2A and 8-pin I2C interface matching connectors, allowing quick setup and evaluation of the circuit performance. The EVAL-CN0372-PMDZ board contains the circuit to be evaluated. The SDP controller board is used in conjunction with the CN0372 Evaluation Software to capture data and present results to the user.
||Connects to AD7091R-5 CONVST/GPO1 pin.
|2, 3, 4||NC||No connection|
|5, 11||GND||Connects to GND|
|6, 12||VDD_PMOD||Connects to PMOD power supply.|
|7||ALERT||Connects to AD7091R-5 ALERT pin.|
|8||RESET||Connects to AD7091R-5 RESET pin.|
|9||PMOD_GPIO1||Connects to ADA4805-1 SHUTDOWN pin. Also connects to ADP5090 DIS_SW pin through SL2.|
|10||PMOD_GPIO2||Connects to ADP5090 PGOOD pin.|
|1, 2||SCL||Connects to AD7091R-5 SCL pin
|3, 4||SDA||Connects to AD7091R-5 SDA pin|
|5, 6||GND||Connects to GND|
|7, 8||VDD_PMOD||Connects to PMOD power supply|
The following equipment is needed
- PC with a USB port and Windows® XP, Windows Vista® (32-bit), or Windows 7 (32-bit)
- EVAL-CN0372-PMDZ circuit evaluation board
- EVAL-SDP-CB1Z SDP controller board
- SDP-PMD-IB1Z interposer board
- 8-pin IDSD-04-D flexible cable: needed to connect the I2C interface between the EVAL-CN0372-PMDZ and SDP-PMD-IB1Z boards (included with the EVAL-CN0372-PMDZ board)
- CN0372 Evaluation Software
- Power supply: 6 V wall wart
- USB cable
- SRS DS360 ultralow distortion function generator or similar precision source
- Cymbet CBC-PV-01 PV cell: typical operating voltage is 0.8 V with an output current of approximately 200 μA at 200 Lux in fluorescent light
Before connecting the boards to the PC, install the CN0372 Evaluation Software. The most up to date version of the evaluation software can be downloaded from ftp://ftp.analog.com/pub/cftl/CN0372. Follow the on-screen prompts to finish the installation. It is recommended to install all software components to the default locations.
Connect the EVAL-CN0372-PMDZ in the desired regulator configuration, and connect the circuit evaluation board to the SDP-PMD-IB1Z interposer board.
Connect the I2C interface on the EVAL-CN0372-PMDZ board to the SDP-PMD-IB1Z interposer board with the 8-pin flexible cable.
Connect the SDP-PMD-IB1Z board to the EVAL-SDP-CB1Z controller board. Apply power to the SDP-PMD-IB1Z board, and connect the EVAL-SDP-CB1Z SDP controller board to the PC via the provided USB cable. Open the evaluation software and start evaluation.
Information regarding the EVAL-SDP-CB1Z can be found in the SDP User Guide (UG-277).
Functional Block Diagram
Figure 11 shows the functional block diagram of the test setup used for evaluating the circuit.
Power Supply Configuration
Connect a low power, high impedance dc source (such as the Cymbet CBC-PV-01 PV cell or TEG) to the J4 terminal, and place SL4 and SL5 in Position A before opening the evaluation software. This makes use of the ADP5090 energy harvesting circuit as system supply. For the complete power supply options available, see Table 4 and Table 5
Table 6 contains the complete description of all solder links on the EVAL-CN0372-PMDZ.
|VDD||Solder Link Position|
|VDrive||Solder Link Position|
|SL1||A||This link is used in conjunction with SL7 connected A to center.
A to center connects the ADP5090 BACK_UP pin to the CR2302 battery.
B to center connects the ADP5090 B_CHRG pin to R36 near the super capacitor.
|SL2||A||This link selects the ADP5090 DIS_SW pin connection.
A to center connects the ADP5090 DIS_SW pin to ground.
B to center connects the ADP5090 DIS_SW pin to PMOD_GPIO1 (Pin 9 of J3).
|SL3||A||This link selects the VDRIVE connection in conjunction with SL4.
A to center connects the ADP5090 SYS pin to VDRIVE.
B to center connects the ADP1607 VOUT pin to VDRIVE.
|SL4||A||This link selects the VDRIVE source.
A to center connects VDD_PMOD to VDRIVE.
B to center connects VDRIVE to either the ADP1607 or ADP5090 output through SL3.
|SL5||A||This link selects the VDD source.
A to center connects the ADP5090 SYS output to VDD.
B to center connects the ADP1607 output to VDD.
|SL6||open||This link selects the VDD_PMOD source when SDP-I-PMOD is not used.
A to center connects the ADP5090 SYS output to VDD_PMOD.
B to center connects the ADP1607 output to VDD_PMOD.
|SL7||A||This link selects the CR2032 battery path.
A to center connects the battery to SL1 to serve as backup (SL1 connected A to center) or to charge the super capacitor (SL1 connected B to center).
B to center connects the battery to the ADP1607 VIN pin.
|SL8||B||This link is used to select the ADP1607 EN pin connection.
A to center connects EN to GND, and turns synchronous boost off.
B to center connects EN to the ADP1607 VIN pin, and turns synchronous boost on.
|SL9||B||This link selects the MUXOUT connection.
A to center connects MUXOUT to the ADA4805-1 inverting input.
B to center connects MUXOUT to the ADA4805-1 noninverting input if SL12 is in Position B.
|SL10||A||This link selects the AS0 connection.
A to center connects AS0 to GND.
B to center connects AS0 to VDRIVE.
|SL11||A||This link selects the AS1 connection.
A to center connects AS1 to GND.
B to center connects AS1 to VDRIVE.
|SL12||B||This link selects the optional buffer.
A to center connects REF to the ADA4805-1 noninverting input.
B to center connects MUXOUT to the ADA4805-1 noninverting input if SL9 is in Position B.
|SL13||A||This link selects the ADA4805-1 SHUTDOWN connection.
A to center connects SHUTDOWN to PMOD_GPIO1.
B to center connects SHUTDOWN to the VDD source selected in SL5.
Setup and Test
After the board is powered up and the evaluation software is initialized, set the ADC to convert at the desired channel. Introduce an input signal at the J1 terminal, click Single Capture or Continuous Capture, and observe the results.
To test the alert function, set Low Limit or High Limit in the evaluation software Configure tab and observe the LED alert indicator outside of the set range.
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