Interfacing to the Fractional T1 and E1


This application note provides an example fractional T1 and E1 circuit design using Analog Devices T1/E1 single chip transceivers (SCTs) and T1/E1 framers.


This application note shows a "looped-timed" application where a Dallas framer or single-chip transceiver (SCT) is configured for a fractional T1/E1 interface.

This application note applies to the following products:

T1 Framers E1 Framers T1 SCTS E1 SCTS T1/E1 SCTS
DS2141 DS2143 DS2151 DS2153 DS2156
DS21Q41 DS21Q43 DS2152 DS2154 DS2155
DS21Q42 DS21Q44 DS21352 DS21354 DS21Q55
DS21FF42 DS21FF44 DS21552 DS21554 DS21455
DS21FT42 DS21FT44 DS21Q552 DS21Q554 DS21458
    DS21Q352 DS21Q354 DS36528

General Configuration

It is common for a T1/E1 carrier subscriber to not have the full T1/E1 rate of service, but a fractional T1 or E1 service, since the full bandwidth may not be needed or affordable. The circuit shown in Figure 1 shows an example of a fractional T1/E1 circuit design, where the application is "looped-timed" and connected to a V.35/RS-449/S530 interface. In this figure, the transmit and receive FT1/E1 streams occupy the same time slots. The DS2175 is our T1/CEPT Elastic Store IC and the XR-T8000 is the Exar Clock Synchronizer/Adaptor for Communications IC. The idle registers on the Dallas framer/SCT can be used to fill unused channels, and the used channels do not need to be contiguous. RCHBLK can be used with TCHBLK to allow up to three additional FT1/E1 ports. Reset should be activated after all the clocks are stable.

Figure 1. Fractional T1/E1 to V.35 interface.

Figure 1. Fractional T1/E1 to V.35 interface.


This application note has shown how to design our framers/SCTs for fractional T1/E1 in a "loop-timed" application.

If you have further questions about fractional T1/E1, please contact the Tech support team.

Dallas Framer/SCT Information

For more information about our framers/SCTs, please consult the data sheets available on our website at