ADRF5592

预发布

Gain Ranging SiP Module, 18GHz to 55GHz

产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许,也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。

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概述

  • Gain ranging with digital step attenuator and amplifier
  • Usable frequency range: 18GHz to 55GHz
  • Integrated active bias and power supply decoupling
  • RF DSA attenuation range : 22dB with 2dB resolution
  • Gain: 17dB typical at 50GHz, minimum attenuation
  • Output P1dB: 27dBm typical at 35GHz
  • Output IP3: 35dBm typical at 35GHz
  • Noise figure: 8dB typical at 35GHz
  • RF input power handling: 22dBm, minimum attenuation
  • CMOS/LVTTL compatible
  • 48-terminal, 8mm × 6mm, LGA package

The ADRF5592 is a gain ranging SiP module that provides a wide band operation from 18GHz to 55GHz. The part includes a digital step attenuator, a power amplifier and a power detector in series. With the integration of active bias circuitry for amplifier, no sequencing is required.

The ADRF5592 provides a typical gain of 17dB amplifier mode in minimum attenuation, with 22dB of gain range and 2dB attenuation resolution. The part requires +3.3V and +5V for the digital step attenuator and the power amplifier. The internal bias controller is capable of generating the negative bias voltage −3.3V via NVG feature. Alternatively, −3.3V can be applied externally by disabling the NVG. The ADRF5592 draws a current of 850mA on the positive supply of 5V and 5mA on negative supply of 3.3V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls.

The ADRF5592 RF ports are designed to match a characteristic impedance of 50Ω. The ADRF5592 is a Figure 5 and can operate between −40°C to +85°C.

APPLICATIONS

  • Test and instrumentation
  • Cellular infrastructure: 5G mmWave
  • Military radios, radars, electronic counter measures (ECMs)
  • Microwave radios and very small aperture terminals (VSATs)

ADRF5592
Gain Ranging SiP Module, 18GHz to 55GHz
ADRF5592 Functional Block Diagram
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