ADA4356

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Programmable Transimpedance, Current to Bits Receiver μModule

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概述

High performance, current input, data-acquisition μModule that includes
- Programmable-gain transimpedance amplifier (PGTIA)
- Fully differential amplifier (FDA)
- Programmable analog low-pass filter (LPF)
- 14-bit 125MSPS ADC
- Three selectable gains
- Integrated 1.8V LDO for the ADC
Small form factor: 12.00mm × 6.00mm BGA
Operation from a single 3.3V supply
PGTIA selectable gains single 20ns pulse sensitivity
- T_Z = 133kΩ, 250nA to 10μA
- T_Z = 11kΩ, 1μA to 100μA
- T_Z = 4.54kΩ, 10μA to 300μA

Optional external current divider circuit enables current detections up to 60mA
Fast input overload recovery
Analog filter for noise reduction and anti-alias filtering
- Selectable 1.0MHz and 100MHz LPF bandwidth
Low input referred current noise: 3.5nA RMS
- T_Z = 133kΩ, 1MHz analog filter
14-bit ADC with sample rate up to 125MSPS
- Serial LVDS data output
- Serial peripheral interface (SPI) controls
Quiescent power: 546mW, LDO enabled
Temperature range: −40°C to +85°C

The ADA4356 is a low-noise, wide dynamic-range, current input, analog-to-digital converter (ADC) μModule. For space savings in size conscious applications, the ADA4356 includes all the required active and passive components to realize a complete current-to-bits data-acquisition solution with programmable gain and filter characteristics.

The high-speed transimpedance amplifier (TIA) front-end amplifier in the ADA4356 supports 20ns pulse widths, which allows high spatial resolution for the ToF measurements, and exhibits fast overdrive recovery from large input signals. The ADA4356 includes three selectable TIA feedback resistor values for programmable TIA gain.

An internal analog low-pass filter offers either 100MHz or 1MHz cutoff frequencies to reduce broadband noise and serve as an anti-aliasing filter for the ADC inputs. For lower bandwidth signals, the 1MHz filter configuration offers additional noise reduction.

Following the TIA and filter blocks, a 14-bit pipeline ADC converts the analog signal at 125MSPS and outputs the digitized signals through two serial, low voltage, differential signaling (LVDS) data lanes operating at rates up to 1GBPS per lane. The data clock output (DCO) operates at frequencies of up to 500MHz and supports double data rate (DDR) operation.

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