ADF4030

推荐用于新设计

10-Channel Precision Synchronizer

数据手册 (Rev. 0) 产品选型表
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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概述

  • 10 BSYNC channels
  • Precise BSYNC time alignment (<5 ps)
  • Enables clock synchronization in large distribution networks
  • Independent programmable BSYNC channel delay
  • Precise path delay compensation of each BSYNC channel using bidirectional loopback capability
  • Flexible physical interface supports PCB trace or cable connections with DC or AC coupling
  • Each BSYNC channel supports gapped periodic clocking
  • Integrated TDC
  • Integrated Temperature Sensor

The ADF4030 provides for 10 bidirectional synchronized clock (BSYNC) channels and accepts a reference clock input (REFIN) signal as a frequency reference for generating an output clock on any BSYNC channels that are configured as an output. The hallmark feature of the ADF4030 is the ability to time align the clock edges of any one or more BSYNC channels to <5 ps (at the device pins) with respect to the BSYNC channel selected as the reference BSYNC channel.

The ADF4030 is well adapted for multiple connections with other ADF4030 devices for synchronizing clock signals in a system. Each BSYNC is bidirectional, allowing for reversing the direction of the clock signal to measure the propagation delay of the transmission medium. Round trip constructions that use replica paths are also supported. The bidirectional nature of the round trip delay measurement greatly reduces the error in determining the propagation delay through the BSYNC transmission medium as compared to using a replica path. This feature makes the ADF4030 capable to time align the clock edges of BSYNC channels across multiple ADF4030 devices, independent of the tree or cascade architecture in which the ADF4030 system is designed. The benefits of bidirectional clocking extend to devices other than the ADF4030 (assuming those devices support bidirectional clock exchanges).

The output divider block associated with each BYSNC channel has an optional pseudorandom binary sequence (PRBS) generator for Rev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT FUNCTIONAL BLOCK DIAGRAM Figure 1. Functional Block Diagram producing gapped periodic clock signals that supports JESD204B and JESD204BC operation.

The ADF4030 may be used as a standalone differential time-to-digital converter (TDC) to measure the difference in time between clocks arriving at the inputs.

The RMS jitter of one ADF4030 BSYNC clock is 4.3 ps typical.

The ADF4030 is available in a 48-lead, 7 mm × 7 mm, land grid array [LGA] package and operates over the −40°C to +105°C ambient temperature range.

Throughout the data sheet, the letter x is used to mean any integer. For example, in BSYNCx, x refers to any channel from Channel 0 to Channel 9.

APPLICATIONS

  • 5G timing transport high precision synchronization
  • Phased array radar
  • Automatic test equipment (ATE) pin electronics
  • JESD204B/JESD204C support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
ADF4030
10-Channel Precision Synchronizer
ADF4030 Functional Block Diagram ADF4030 Pin Configuration
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参考资料

数据手册 1

技术文章 1

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软件资源

器件驱动器 2

硬件生态系统

部分模型 产品周期 描述
开关稳压器和控制器 1
LTM8053
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ADP7159
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2 A、超低噪声、高PSRR、可调输出、RF线性稳压器
ADP7112
推荐用于新设计 20 V、200 mA低噪声CMOS LDO线性稳压器
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工具及仿真模型

IBIS 模型 1

LTspice

LTspice®是一款强大高效的免费仿真软件、原理图采集和波形观测器，为改善模拟电路的仿真提供增强功能和模型。

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eval board
schematic 1
schematic 2
schematic 3
schematic 4
EVAL-ADF4030

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特性和优点

  • EV-ADF4030SD1Z evaluation board including the ADF4030 10channel precision synchronizer, Arduino interface, and voltage regulators
  • Allows multiple ways to provide a reference clock to the ADF4030
    • Single-ended from a signal generator
    • Differential from another device or additional ADF4030 devices
  • Gives access to all 10 ADF4030 BSYNC bidirectional I/O lines using twinax and SMA connectors
  • Facilitates interfacing the ADF4030 clocks with an oscilloscope or other boards using an interposer board
  • SDP-K1 controller board functions as an interface between a PC and the evaluation board
  • Up to 16 EV-ADF4030SD1Z evaluation boards can be stacked up using the Arduino connector
  • Windows®-based software allows control of all ADF4030 functions from a PC

产品详情

The EV-ADF4030SD1Z evaluates the performance of the ADF4030 10-channel precision synchronizer. The SDP-K1 controller board must be connected to the EV-ADF4030SD1Z using the Arduino connector underneath the evaluation board. Multiple EVADF4030SD1Z evaluation boards can be stacked up onto the SDP-K1 controller board using the Arduino connector.

A photograph of the evaluation board with the SDP-K1 controller board is shown in Figure 1. The evaluation board contains the ADF4030 10-channel precision synchronizer, the power supply connectors, and the Arduino connector used to connect to the SDP K1 board. This combination allows software programming of the evaluation board using ACE software.

Full specifications for the ADF4030 precision synchronizer are available in the product data sheet, which must be consulted in conjunction with this user guide when working with the evaluation board.

ADXBAND16EBZ

16Tx/16Rx Direct X-Band Sampled Phased-Array/RADAR/SATCOM Development Platform

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特性和优点

ADXBAND16EBZ Digitizing Card
  • Multi-Channel, Wideband System Development Platform Using Apollo (AD9084)
  • Mates With Xilinx VCU118 Evaluation Board (Not Included)
  • 16x RF Receive (Rx) Channels
    • Total 16x 8GSPS to 20GSPS ADC
    • Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
    • Programmable Finite Impulse Response Filters (pFIRs)
    • Complex Finite Impulse Response Filters (CFIRs)
  • 16x RF Transmit (Tx) Channels
    • Total 16x 8GSPS to 28GSPS DAC
    • Digital Up Converters (DUCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
    • Programmable Finite Impulse Response Filters (pFIRs)
    • Complex Finite Impulse Response Filters (CFIRs)
  • Flexible Rx & Tx RF Front-Ends
    • Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
    • Tx: Filtering, Amplification
  • Flexible Clock Distribution
    • On-Board Clock Distribution from Single External 400MHz Reference
    • Support for External Converter Clock per AD9084 via solder rework
  • On-Board Power Regulation from Single 12V Power Adapter (Included)
16Tx / 16Rx Calibration Board
  • Mates to ADXBAND16EBZ Digitizing Card & VCU118 PMOD Interface (Cable Included)
  • Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
  • Combined Tx Channels Out Option
  • Combined Rx Channels In Option
Software Features and Benefits

Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:

  • IIO Oscilloscope GUI
  • MATLAB Add-Ons & Example Scripts
  • Example HDL Builds including JESD204C Bring-Up
  • Embedded Software Solutions for Linux and Device Drivers
Software Reference Design Examples for ADEF Applications to Reduce Prototyping Time:
  • Multi-Chip Synchronization for Power-Up Phase Determinism
  • System-Level Amplitude/Phase Alignment Using NCOs
  • Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
  • pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
  • Fast-Frequency Hopping

产品详情

The ADXBAND16EBZ contains four AD9084 mixed‑signal front‑end devices, including the RF front end, clocking, and power circuitry. The ADXBAND16EBZ serves as a complete system solution targeting common applications such as phased‑array radars, wideband systems, and ground‑based SATCOM. Its primary target application is a 16‑Tx/16‑Rx direct X‑band sampling phased array.

The platform is intended as a testbed for demonstrating multi‑chip synchronization, as well as implementing system‑level calibrations, beamforming algorithms, and other signal‑processing techniques. The system is designed to interface with the VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, along with provided reference software, HDL code, and MATLAB system‑level interfaces.

A 16‑Tx/16‑Rx Calibration Board can be used to develop system‑level calibration algorithms, including demonstrations of power‑up phase determinism. The Calibration Board provides improvements in combined‑channel dynamic range, spurious performance, and phase noise, and can be controlled via a MATLAB add‑on when connected to the PMOD interface of the VCU118.
EVAL-ADF4030
EVAL-ADF4030 Angle View EVAL-ADF4030 Bottom View EVAL-ADF4030 Top View EVAL-ADF4030 with SDP-K1
ADXBAND16EBZ
16Tx/16Rx Direct X-Band Sampled Phased-Array/RADAR/SATCOM Development Platform

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