ADF4030

• EV-ADF4030SD1Z 评估板包括 ADF4030 10 通道精密同步器、Arduino 接口和电压调节器
• 允许通过多种方式为 ADF4030 提供参考时钟
  • 来自信号发生器的单端
  • 与另一台设备或其他 ADF4030 设备的差分
• 使用双绞线和 SMA 连接器访问所有 10 条 ADF4030 BSYNC 双向 I/O 线路
• 方便使用中介板将 ADF4030 时钟与示波器或其他电路板连接
• SDP-K1 控制器板可作为 PC 和评估板之间的接口
• 使用 Arduino 连接器最多可以堆叠 16 个 EV-ADF4030SD1Z 评估板
• 基于 Windows^® 的软件允许通过 PC 控制 ADF4030 的所有功能

EV-ADF4030SD1Z 评估 ADF4030 10 通道精密同步器的性能。必须使用评估板下方的 Arduino 连接器将 SDP-K1 控制器板连接到 EV-ADF4030SD1Z。可以使用 Arduino 连接器将多个 EV-ADF4030SD1Z 评估板堆叠到 SDP-K1 控制器板上。

图 1 显示了带有 SDP-K1 控制器板的评估板的照片。该评估板包含 ADF4030 10 通道精密同步器、电源连接器以及用于连接 SDP K1 板的 Arduino 连接器。这种组合允许使用 ACE 软件对评估板进行软件编程。

产品数据手册中包含 ADF4030 精密同步器的完整规格说明，使用评估板时必须同时参阅产品数据手册和本用户指南。

• Transmit and receive frequency X band: 8GHz to 12GHz
• Direct sampling in L, S, and C bands with capacitor rotation
• Multichannel, wideband system development platform for the AD9084 
• Mates with Xilinx VCU118 evaluation board (must be purchased separately)
• 16× RF receive channels (32× digital receive channels)
  • Total 16× 4GSPS to 20GSPS ADC channels
  • 48× digital downconverters (DDCs) and complex NCOs
  • 16× programmable finite impulse response filters (pFIRs)
  • 16× complex finite impulse response filters (CFIRs)
• Complete power management solution for all domains
• Single 12V supply voltage for easy power management
• Board size: 221mm × 158mm (8.9” × 6.2”)

This user guide serves as the main source of information for system engineers and software developers using the ADXBAND16EBZ. This platform contains four AD9084 software-defined, direct sampling mixed-signal front end (MxFE), including an RF front end, clocking, and power circuitry. Common target applications are phased array radars, electronic warfare, and ground-based SATCOM. The receive and transmit RF front ends have bypass configurations that allow customized frequency ranges of less than 8GHz up to 18GHz.

The ADXBAND16EBZ highlights a complete system solution. This platform is intended as a testbed for demonstrating multichip synchronization as well as the implementation of system-level calibrations and signal processing algorithms. The system is designed to mate with a Xilinx VCU118 evaluation board, which features the Virtex UltraScale+ XCVU9P field-programmable gate array (FPGA), with provided reference software, hardware design language (HDL) code, and MATLAB system-level interfacing.

A 16 transmit and 16 receive calibration board (ADXBAND16EBZCAL) can be used to develop system-level calibration algorithms to demonstrate power-up phase determinism. The calibration board demonstrates combined-channel dynamic range, spurious, and phase noise improvements that can also be controlled via a MATLAB add-on when connected to the peripheral module (PMOD) interface of the VCU118.

APPLICATIONS

• Phased-array, radar, electronic warfare, and satellite communications (SATCOM)
• Communications infrastructure (multiband and mmWave 5G)
• Electronic test and measurement