AD4086

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14-Bit, 40 MSPS, Low Noise, Low Power SAR ADC

产品模型: 3

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概述

14-bit resolution, no missing codes
Throughput: 40MSPS, 48.21ns conversion latency
Noise spectral density: 24.18nV/√Hz,158.9dBFS/Hz
Low 1/f, low frequency noise (0.1Hz to 10Hz): 396nV rms
Low Power:85mW typical at 40MSPS
INL: ±12ppm (typ), ±16ppm (max)
Dynamic range: 85.85dBFS
SNR/THD
- 85.34dB (typ)/−110.4dB (typ) at f_IN = 1kHz
- 85.27dB (typ)/−101.3dB (typ) at f_IN = 1MHz
Easy Drive
- 6V p-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current
Integrated, low-drift reference buffer and decoupling

Integrated V_CM generation
Digital features and data interface
- Conversion result FIFO, 16K sample depth
- Digital averaging filter with up to 2¹⁰ decimation
SPI configuration
Configurable data interface
- Single lane, DDR, serial LVDS, 560Mbps per lane
- Dual lane, DDR, serial LVDS, 280Mbps per lane
- Single/quad lane SPI data interface
Package
- 49-ball, 5mm × 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
Operating temperature range: −40°C to +85°C

The AD4086 is a high speed, low noise, low distortion, 14-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 90dBFS) at signal frequencies in excess of 1MHz enables the AD4086 to service a wide variety of precision, wide bandwidth data acquisition applications. Simplification of the input anti-alias filter design can be accomplished by applying oversampling along with the integrated digital filtering and decimation to reduce noise and lower the output data rate for applications that do not require the lowest latency of the AD4086.

The AD4086 Easy Drive features reduce both signal chain complexity and power consumption while enabling greater channel density and flexibility in companion component selection. The product input structure was designed to minimize any input dependent signal currents, therefore reducing any converter induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements as compared to other high-speed data converters.

The AD4086 includes several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regulators to generate ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can greatly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated in the package to ensure optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint.

APPLICATIONS

Digital imaging
Cell analysis
Spectroscopy
Automated test equipment
High speed data acquisition
Digital control loops, hardware in the loop
Power quality analysis
Source measurement units
Electron and X-ray microscopy
Radar level measurement
Nondestructive test

产品模型: 3

参考资料

数据手册 1

AD4086: 14-Bit, 40 MSPS, Low Noise, Low Power SAR ADC Data Sheet (Rev.0) 02/05/2026

用户手册 1

EVAL-AD4086 User Guide: Evaluating the AD4086/AD4087 14-Bit, 40/20 MSPS, Differential SAR ADC (Rev.0) 02/05/2026

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产品型号	引脚/封装图-中文版	文档	CAD 符号，脚注和 3D模型
AD4086BBCZ	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report 资料包	Ultra Librarian SamacSys
AD4086BBCZ-RL	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report 资料包	Ultra Librarian SamacSys
AD4086BBCZ-RL7	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report 资料包	Ultra Librarian SamacSys

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软件资源

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评估套件

Evaluating the AD4086/AD4087 14-Bit, 40/20 MSPS, Differential SAR ADC

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特性和优点

Full featured evaluation board for AD4086/AD4087
Analysis | Control | Evaluation (ACE) Software plugin available for device configuration, data capture, and performance evaluation
Flexible analog front end
On-board power solution and precision reference
On-board clock generation circuitry with sampling frequency control via the ACE software
FMC compatible

产品详情

The EVAL-AD4086-FMCZ is designed to demonstrate the performance of the AD4086 analog‐to‐digital converter (ADC) and provide access to a limited set of device configuration features through the ACE Software environment. The EVAL-AD4086-FMCZ evaluation kit supports the following AD4086 features:

Low voltage digital signaling (LVDS) data output interface.
ADC configuration via serial peripheral interface (SPI).
Internal or external generation of 1.1V regulated supply rails.
Sampling rate capability between 1.25MSPS and up to 40MSPS, depending on the specific ADC.

The EVAL-AD4086-FMCZ evaluation board was designed for use with the Digilent ZedBoard via the field programmable gate array (FPGA) mezzanine card (FMC) connector. The ZedBoard uses a Xilinx Zynq7000 system on chip (SoC) running Analog Devices, Inc., Kuiper Linux and LIBIIO (included on the SD card supplied in the evaluation board kit) to facilitate communication with the EVAL-AD4086-FMCZ, enabling ADC configuration, capturing data, and providing the communication link to the host PC and the ACE Software plugin.

The AD4086 that is physically mounted on the board can be evaluated with any sampling frequency range from 1.25MHz to 40MHz. However, performance of the AD4087 can also be estimated using this board by setting the sampling frequency to 20MHz. Note, the captured results for AD4086 running at the reduced sample rate should only be taken as indications of the signal-to-noise ratio (SNR) rather than the actual measurement; nevertheless, measured SNR for the AD4087 will not be worse.

资料

EVAL-AD4086 User Guide: Evaluating the AD4086/AD4087 14-Bit, 40/20 MSPS, Differential SAR ADC (Rev.0)
2026/2/5