AD9697
RECOMMENDED FOR NEW DESIGNS14-Bit, 1300 MSPS, JESD204B, Analog-to-Digital Converter
- Part Models
- 2
- 1ku List Price
- Starting From $562.61
Overview
- JESD204B (Subclass 1) coded serial digital outputs
- Lane rates up to 16 Gbps
- 1.01 W total power at 1300 MSPS
- SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)
- SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)
- Noise density
- −153.9 dBFS/Hz (1.59 V p-p input range)
- −155.6 dBFS/Hz (2.04 V p-p input range)
- 0.95 V, 1.8 V, and 2.5 V supply operation
- No missing codes
- Internal ADC voltage reference
- Flexible input range
- 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)
- 2 GHz usable analog input full power bandwidth
- Amplitude detect bits for efficient AGC implementation
- 4 integrated digital downconverters
- 48-bit NCO
- Programmable decimation rates
- Differential clock input
- SPI control
- Integer clock divide by 2 and divide by 4
- Flexible JESD204B lane configurations
- On-chip dithering to improve small signal linerarity
The AD9697 is a single, 14-bit, 1300 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9697 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/ output (GPIO) pins, or to use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9697 between the DDC modes is selectable via serial port interface (SPI)programmable profiles.
In addition to the DDC blocks, the AD9697 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9697 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.
The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9697 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire SPI and or PDWN/STBY pin.
The AD9697 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +105°C junction temperature (TJ) range. This product may be protected by one or more U.S. or international patents.
Note that, throughout this data sheet, a multifunction pin, FD/GPIO1, is referred to either by the entire pin name or by a single function of the pin, for example, FD, when only that function is relevant.
Product Highlights
- Low power consumption
- JESD204B lane rate support up to 16 Gbps
- Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz
- Buffered inputs ease filter design and implementation
- Four integrated wideband decimation filters and NCO blocks supporting multiband receivers
- Programmable fast overrange detection
- On-chip temperature diode for system thermal management
Applications
- Communications
- Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation
- Oscilloscopes
- Spectrum analyzers
- Network analyzers
- Integrated RF test solutions
- Radars
- Electronic support measures, electronic counter measures, and electronic counter to counter measures
- High speed data acquisition systems
- DOCSIS 3.0 CMTS upstream receive paths
- Hybrid fiber coaxial digital reverse path receivers
- Wideband digital predistortion
Documentation
Device Drivers 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9697BCPZ-1300 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) | ||
| AD9697BCPZRL7-1300 | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 1
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
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Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock ICs 6 | ||
| LTC6951 | LAST TIME BUY | Ultralow Jitter Multi-Output Clock Synthesizer with Integrated VCO |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | NOT RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| AD9528 | RECOMMENDED FOR NEW DESIGNS | JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| HMC7043 | NOT RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| Fanout Buffers 1 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
Tools & Simulations
ADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open Tool