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ADCLK925:  超快型SiGe ECL时钟/数据缓冲器

产品详情

产品状态:推荐用于新设计

ADCLK905(单输入/单输出)、ADCLK907(双通道单输入/单输出)和ADCLK925(单输入/双输出)为超高速时钟/数据缓冲器,采用ADI公司专有的XFCB3硅锗(SiGe)双极性工艺制造。

ADCLK905/ADCLK907/ADCLK925内置全摆幅射极耦合逻辑(ECL)输出驱动器。对于PECL(正ECL)工作模式,将VCC偏置至正电源,将VEE 偏置至接地。对于NECL(负ECL)工作,VCC偏置至接地,VEE 偏置到负电源。

缓冲器具备95 ps的传播延迟、7.5 GHz的触发率、10 Gbps的数据速率以及60 fs的随机抖动(RJ)。

输入含有100 Ω的中心抽头片内端接电阻。提供VREF引脚用于偏置交流耦合输入。

ECL输出级旨在从各端将800 mW直接驱动至端接于VCC − 2 V的50 Ω负载,从而获得1.6 V的总差分输出摆幅

ADCLK905/ADCLK907/ADCLK925提供16引脚LFCSP封装。

应用

  • 时钟和数据信号恢复和电平转换
  • 自动测试设备(ATE)
  • 高速仪器仪表
  • 高速线路接收机
  • 阈值检测
  • 转换器时钟
  • 特点和优势

    • 传播延迟:95 ps
    • 反转率:7.5 GHz
    • 典型输出上升/下降:60 ps
    • 随机抖动(RJ):60 fs
    • 两个输入引脚上均有片内端电极
    • 扩展工业温度范围:−40°C至+125°C
    • 电源:2.5 V至3.3 V (VCC – VEE)

    ADCLK925 功能框图

    文档

    快讯名称 内容类型 文件类型
    ADCLK905/ADCLK907/ADCLK925: Ultrafast SiGe ECL Clock/Data Buffers Data Sheet (Rev 0, 08/2007) (pdf, 1097 kB) 产品数据手册 PDF
    AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号  (pdf, 0) 应用笔记 PDF
    AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal  (pdf, 221 kB) 应用笔记 PDF
    AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版]  (pdf, 234 kB) 应用笔记 PDF
    AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)  (pdf, 170 kB) 应用笔记 PDF
    AN-873: ADF4xxx系列PLL频率合成器的锁定检测  (pdf, 0) 应用笔记 PDF
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers  (pdf, 207 kB) 应用笔记 PDF
    AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版]  (pdf, 416 kB) 应用笔记 PDF
    AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance  (pdf, 313 kB) 应用笔记 PDF
    AN-823: 时钟应用中的直接数字频率合成器[中文版]  (pdf, 303 kB)
    基于直接数字频率合成器的时钟系统的时间抖动
    应用笔记 PDF
    AN-823: Direct Digital Synthesizers in Clocking Applications Time  (pdf, 115 kB)
    Jitter in Direct Digital Synthesizer-Based Clocking Systems
    应用笔记 PDF
    AN-769: 基于AD9540产生多时钟输出  (pdf, 130 kB) 应用笔记 PDF
    AN-769: Generating Multiple Clock Outputs from the AD9540  (pdf, 0) 应用笔记 PDF
    AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版]  (pdf, 808 kB) 应用笔记 PDF
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) 应用笔记 PDF
    AN-741: 鲜为人知的相位噪声特性  (pdf, 359 kB) 应用笔记 PDF
    AN-501: 孔径不确定度与ADC系统性能[中文版]  (pdf, 227 kB)
    在中频采样中的一个关键问题是孔径不确定度(抖动)
    应用笔记 PDF
    AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
    A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
    应用笔记 PDF
    CN-0290:扩展高性能锁相环的低频范围  (pdf, 406 kB) Circuit Note PDF
    MT-008: 将振荡器相位噪声转换为时间抖动  (pdf, 123 kB) 技术指南 PDF
    UG-582: Evaluating the EVAL-CN0290-SDPZ  (pdf, 306 kB) 用户指导 PDF
    UG-006:设置ADCLK905/ADCLK907/ADCLK925评估板  (pdf, 335 kB) 用户指导 PDF
    Speedy A/Ds Demand Stable Clocks
    by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
    技术文章 HTML
    Design A Clock-Distribution Strategy With Confidence
    by Demetrios Efstathiou (Electronic Design, April 27, 2006)
    技术文章 HTML
    Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
    ... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
    by Brad Brannon, Analog Devices (EDN, 12/7/2004)
    技术文章 HTML
    Clock Requirements For Data Converters
    (Electronic Design, 2/2005)
    技术文章 HTML
    高速转换器时钟分配器件的端接[中文版]
    (其它技术文章,2010年1月)
    《模拟对话》杂志 HTML
    模数转换器时钟优化:测试工程观点 [中文版]
    (模拟对话, 第42卷,2008年2月)
    《模拟对话》杂志 HTML
    Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective  (pdf, 909 kB)
    By Rob Reeder, Wayne Green, and Robert Shillito
    技术资料 PDF
    RF 手册  (pdf, 988 kB)
    RF IC 选型指南(12/2010)
    概况 PDF
    Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks  (pdf, 64 kB) 概况 PDF
    Reset your thinking about clocks.  (pdf, 153 kB)
    ... In precision timing, analog is everywhere.
    概况 PDF
    Clock and Timing ICs  (pdf, 4970 kB) 概况 PDF
    数模转换器IC 解决方案,第10卷 • 第1期  (pdf, 2912 kB) 解决方案通报 PDF
    Why do I see reference spurs? 常见问题解答 HTML
    Why is my phase noise shape changing when I change the PLL settings? 常见问题解答 HTML
    Why doesn't the PLL make my reference input and the clock outputs line up? 常见问题解答 HTML
    How do I optimize my PLL loop for the best phase noise and/or jitter? 常见问题解答 HTML
    My loop is not locking. How do I debug this? 常见问题解答 HTML
    How long does it take for the PLL to lock? 常见问题解答 HTML
    Help! My PLL came unlocked over temperature. 常见问题解答 HTML
    How do I choose between active and passive filter in PLL loop? 常见问题解答 HTML
    Should I reference the passive filter to ground? or supply? 常见问题解答 HTML
    How do the PLLs in the AD951x parts compare to other ADI PLLs? 常见问题解答 HTML
    How does the clock clean-up function of the AD951x parts work? 常见问题解答 HTML
    Why do I want to run a fast PFD frequency? 常见问题解答 HTML
    Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? 常见问题解答 HTML
    Why can't I use a bandpass filter for my loop filter? 常见问题解答 HTML
    Should I tie my loop filter to ground or PLL supply? 常见问题解答 HTML
    The loop filter was working great until I changed the divide ratio in PLL. What happened? 常见问题解答 HTML
    How do I use a VCO with a supply greater than 5V? 常见问题解答 HTML
    What suppliers do you recommend for VCO/VCXOs? 常见问题解答 HTML
    Do VCXOs have better phase noise and jitter performance than VCOs? 常见问题解答 HTML
    How do I know which VCO will work best with the AD9510? 常见问题解答 HTML
    Is there an advantage to running a higher VCO frequency than the output frequency? 常见问题解答 HTML
    How do I determine if a VCO is good enough for my purpose? 常见问题解答 HTML
    Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? 常见问题解答 HTML
    Do different divide ratios cause variations in jitter? 常见问题解答 HTML
    I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? 常见问题解答 HTML
    Do divide ratios change the propagation delay? 常见问题解答 HTML
    I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? 常见问题解答 HTML
    On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? 常见问题解答 HTML
    Why doesn't the mini-divider support the divide ratio I want? 常见问题解答 HTML
    I want to use the variable delay adjust, but the jitter is too high. What can I do? 常见问题解答 HTML
    I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? 常见问题解答 HTML
    What is the difference between the coarse phase adjust and the fine delay adjust? 常见问题解答 HTML
    What is the fine delay adjust which is available on certain LVDS/CMOS outputs? 常见问题解答 HTML
    Does the fine delay adjust affect the jitter? 常见问题解答 HTML
    Why is the fine delay adjust not available on all the outputs? 常见问题解答 HTML
    Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? 常见问题解答 HTML
    Will the AD9510 work without a reference input signal? 常见问题解答 HTML
    What are the best clock sources for a distribution-only design? 常见问题解答 HTML
    I am not using the CLK1 input on the AD9510. Can I just leave it floating? 常见问题解答 HTML
    How good does my input signal need to be? 常见问题解答 HTML
    I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. 常见问题解答 HTML
    Can I shift the threshold on clocks for single-ended inputs? 常见问题解答 HTML
    The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? 常见问题解答 HTML
    Will differential or single-ended inputs/outputs improve my jitter? 常见问题解答 HTML
    Why should I use differential rather than single-ended? 常见问题解答 HTML
    How do I feed a single-ended signal into a differential input? 常见问题解答 HTML
    Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? 常见问题解答 HTML
    Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? 常见问题解答 HTML
    Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? 常见问题解答 HTML
    On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? 常见问题解答 HTML
    I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? 常见问题解答 HTML
    Can I use the 951X clocks to drive a mixer (RF LO)? 常见问题解答 HTML
    My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? 常见问题解答 HTML
    I have an input present at the clock input, but I'm not seeing an output? 常见问题解答 HTML
    What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? 常见问题解答 HTML
    What clock frequency comes out of the AD9510 outputs when you first apply power to the device? 常见问题解答 HTML
    Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) 常见问题解答 HTML
    I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? 常见问题解答 HTML
    What should I do with unused channels on the AD9510? 常见问题解答 HTML
    Can I tri-state the AD9510 outputs? 常见问题解答 HTML
    On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? 常见问题解答 HTML
    What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? 常见问题解答 HTML
    Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? 常见问题解答 HTML
    What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? 常见问题解答 HTML
    Does the AD9510 support 2.5V PECL? 常见问题解答 HTML
    How much bandwidth is required to process a PECL or LVDS output? 常见问题解答 HTML
    If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? 常见问题解答 HTML
    If I change the level of PECL output, does it affect the jitter? 常见问题解答 HTML
    What is the best way to terminate LVPECL outputs to get lowest jitter? 常见问题解答 HTML
    Is it okay to AC-couple PECL or LVDS outputs? 常见问题解答 HTML
    What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? 常见问题解答 HTML
    What is the proper termination (value and location) for outputs? 常见问题解答 HTML
    Are outputs short-circuit protected? 常见问题解答 HTML
    Are the CMOS drivers on the clock devices complementary? 常见问题解答 HTML
    Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? 常见问题解答 HTML
    I have pulled SYNCB low, but I still have output from a channel. Why? 常见问题解答 HTML
    Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? 常见问题解答 HTML
    The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? 常见问题解答 HTML
    May I use the AD9540 for spread spectrum clocking? 常见问题解答 HTML
    Can I get two clock outputs from the AD9540? 常见问题解答 HTML
    What's the advantage of a DDS-based clock generator? 常见问题解答 HTML
    Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? 常见问题解答 HTML
    I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? 常见问题解答 HTML
    On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? 常见问题解答 HTML
    How do you determine the bandwidth over which phase noise is integrated to obtain jitter? 常见问题解答 HTML
    Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? 常见问题解答 HTML
    How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? 常见问题解答 HTML
    When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? 常见问题解答 HTML
    How do you specify jitter? 常见问题解答 HTML
    How do I use the clock part for jitter clean-up? 常见问题解答 HTML
    If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? 常见问题解答 HTML
    Does jitter vary with different clock frequencies? How about phase noise? 常见问题解答 HTML
    I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? 常见问题解答 HTML
    Do you guarantee performance shown in ADIsimCLK? 常见问题解答 HTML
    Who do I contact for technical support on ADIsimCLK? 常见问题解答 HTML
    Should I use the minimum charge pump current settings in order to minimize power? 常见问题解答 HTML
    Can I run CMOS outputs at 5V? 常见问题解答 HTML
    Can I use different power supply voltages for the PECL output drivers? 常见问题解答 HTML
    Is .01 uF sufficient for power supply pin bypass? 常见问题解答 HTML
    My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? 常见问题解答 HTML
    Why don't you spec psrr and cmrr in the datasheet? 常见问题解答 HTML
    How do I get two AD951x (with PLL) to synchronize to the same reference input edge? 常见问题解答 HTML
    I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? 常见问题解答 HTML
    How do I synchronize multiple clock devices? 常见问题解答 HTML
    What happens if I run the part in an ambient environment which exceeds 85°C? 常见问题解答 HTML
    How can I determine the die temperature of your device? 常见问题解答 HTML
    My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? 常见问题解答 HTML
    What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? 常见问题解答 HTML
    RAQs index 非常见问题解答 HTML
    术语表 专业词汇表 HTML

    设计工具,模型,驱动及软件

    快讯名称 内容类型 文件类型
    ADIsimCLK™设计与评估软件
    ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
    ADIsim Design/Simulation Tools HTML
    ADCLK925 IBIS Model IBIS 模型 HTML

    评估套件,原理图符号和PCB封装

    评估板和开发套件查看评估板和套件页面以了解文档和采购信息

    原理图符号和PCB封装— ADI公司提供与当今众多CAD系统兼容的原理图符号和PCB封装(Symbols & Footprints),以便更广泛、更轻松地使用。

    产品推荐及参考设计

    精确设计,严谨验证,即取即用。
    了解更多

    Sample样片申请及购买

    价格,封装及供货状态

    ADCLK925 型号选项
    产品型号 封装 引脚 温度范围 包装和数量 报价*(100-499) 报价*1000 pcs RoHS 查看PCN/PDN 查看库存/
    购买/样片
    ADCLK925BCPZ-R2 产品状态: 量产 16 ld LFCSP (3x3mm, 1.50mm exposed pad) 16 工业 Reel, 250 $ 6.29 $ 6.29 Y  材料信息 查看PCN 订购
    ADCLK925BCPZ-R7 产品状态: 量产 16 ld LFCSP (3x3mm, 1.50mm exposed pad) 16 工业 Reel, 1500 - $ 5.35 Y  材料信息 查看PCN 订购
    ADCLK925BCPZ-WP 产品状态: 量产 16 ld LFCSP (3x3mm, 1.50mm exposed pad) 16 工业 Tray, 50 $ 6.29 $ 5.35 Y  材料信息 通知我 订购
    帮助

    这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与您当地的ADI公司办事处或代理商联络。对于评估板和套件的报价是指一个单位价格。

    ADCLK925评估板
    产品型号 描述 报价 RoHS 查看PCN/PDN 查看库存/
    购买/样片
    ADCLK925/PCBZ 产品状态: 量产 Evaluation Board $ 190.00 -

    所示报价为单片价格。所列的美国报价单仅供预算参考,指美元报价(每片美国离岸价),如有修改,恕不另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。

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