The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates two completely independent output clocks that are synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.
For convenience, detailed information from the AD9559 data sheet has been included here. Use this user guide in conjunction with the AD9559 data sheet and software documenta¬tion available at www.analog.com.Features