JESD204B Clock Generator with 14 LVDS/HSTL Outputs
The AD9528 is a two-stage PLL with an integrated JESD204B SYSREF generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices.
The AD9528 generates two outputs (Output 1 and Output 2) with a maximum frequency of 1.25 GHz, and 12 outputs up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks.
Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function where applicable.
- High performance wireless transceivers
- LTE and multicarrier GSM base stations
- Wireless and broadband infrastructure
- Medical instrumentation
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B
- Low jitter, low phase noise clock distribution
- ATE and high performance instrumentation
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The AD-FMCADC4-EBZ is a high speed 4-channel data acquisition board featuring two AD9680 dual channel ADC at 1000 MSPS and four ADA4961 low distortion, 3.2 GHz, RF DGA driving each converter. The FMC form factor supports the JESD204B high speed serial interface. All clocking and channel synchronization is support on-board using the AD9528 clock generator. This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9680 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and jamming/anti-jamming measures.
The board meets most of the FMC specifications in terms of mechanical size, mounting hole locations, and more. Although this board does meet most of the FMC specifications, it’s not meant as a commercial off the shelf (COTS) board. If you want a commercial, ready to integrate product, please refer to one of the many FMC manufacturers and the FMC specification (ANSI/VITA 57.1).
This board is targeted to use the ADI reference designs that work with Xilinx development systems. ADI provides complete source (HDL and software) to re-create those projects (minus the IP provided by the FPGA vendors, which we use), but may not provide enough info to port this to your custom platform.
The design of the board is specifically tailored to synchronizing multiple AD-FMCADC4-EBZ boards together. For more information on synchronization please refer to A Test Method for Synchronizing Multiple GSPS Converters. The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring its internal registers via SPI.
The ADRV9375-N/PCBZ is a radio card designed to showcase the AD9375, the first wideband RF transceiver with integrated DPD targeting 3G/4G small cell and massive MIMO. The radio card provides a single 2x2 transceiver platform for device evaluation and rapid prototyping of radio solutions. All peripherals necessary for the radio card to operate including a high efficiency switcher only power supply solution, and a high performance clocking solution are populated on the board. In addition, a 3rd party PA evaluation card is included in the package for DPD evaluation.
The ADRV9371-N/PCBZ and ADRV9371-WPCBZ are radio cards designed to showcase the AD9371, a high performance wideband integrated RF transceiver intended for use in RF applications such as 4G basestation, test and measurement applications and software defined radios. The radio cards provide hardware engineers, software engineers and system architects with a single 2x2 transceiver platform for device evaluation and rapid prototyping of radio solutions. All peripherals necessary for the radio card to operate including a high efficiency switcher only power supply solution, and a high performance clocking solution are populated on the board.
Both narrow tuning range and wide tuning range options exist.
The ADRV9371-N/PCBZ is optimized for performance over a narrow tuning range1.8GHz – 2.6GHz. It will exhibit diminished RF performance on tuned RF frequencies outside of this band. This board is primarily intended to provide RF engineers with the ability to connect the AD9371 to an RF test bench (Vector Signal Analyzer, Signal Generator, etc) and achieve its optimum performance.
The ADRV9371-W/PCBZ operates over a wide tuning range 300MHz – 6GHz, however the RF performance is tempered by the very wide band front end match. This board is primarily intended for system investigation and bringing up various waveforms from a software team before custom hardware is complete. The objective being for designers to see waveforms, but not being concerned about the last 1dB or 1% EVM of performance.
The board interfaces to the Xilinx ZC706 motherboard (EK-Z7-ZC706-G) (ordered separately).
The reference design includes all components necessary for the small cell radio, from the SERDES interface right up to the antenna. The design is suitable for indoor small cells with 2x2, LTE20 250mW output power per antenna. All radio components are on board, including the AD9375 with DPD, high efficiency PAs, LNAs, Filters and a power solution. The power consumption is <10W and it comes in a very small form factor, sitting comfortably in your hand. A Single 12V supply is all that is required to power the board. Plus, it comes with an evaluation kit that connects to a baseband sub-system directly.
JESD204 Serial Interface
The JESD204 and the JESD204B revision data converter serial interface standard was created through the JEDEC...
A Test Method for Synchronizing Multiple GSPS Converters
Clocking Wideband GSPS JESD204B ADCs
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
- 25 week(s) ago in Clock and Timing
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