Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers
Figure 1. ADF4351 PLL Connected to ADCLK948 Fanout Buffer (Simplified Schematic: All Connections and Decoupling Not Shown)
Modern digital systems often require many high quality clocks at logic levels that are different from the logic level of the clock source. Extra buffering may be required to guarantee accurate distribution to other circuit components without loss of integrity. The interface between the ADF4351 clock source ADCLK948 clock fanout buffer is described, and measurements show that the additive jitter associated with the clock fanout buffer is 75 fs rms.
For clock generation, the ADF4351 PLL and VCO must be enabled, and the desired output frequency must be programmed. The output frequency of the ADF4351 is available at the open-collector outputs at the RFOUT pins, which require a shunt inductor (or resistor), plus a dc blocking capacitor.
The ADCLK948 is a SiGe low jitter clock fanout buffer that is ideally suited for use with the ADF4351, because its maximum input frequency (4.5 GHz) is just above that of the ADF4351 (4.4 GHz). Broadband rms additive jitter is 75 fs.
It is necessary to add a dc common-mode bias level of 1.65 V to the CLK inputs of the ADCLK948 to mimic LVPECL logic levels. This is accomplished by the use of a resistor bias network. Omission of the dc bias circuit results in degraded signal integrity at the ADCLK948 outputs.
The following equipment is needed:
- The EVAL-ADF4351EB1Z evaluation board kit with programming software
- The ADCLK948/PCBZ evaluation board
- A 3.3 V power supply
- Two cables to connect the 3.3 V supply to the ADCLK948/PCBZ
- Two short equal length SMA coaxial cables
- A high speed oscilloscope (2 GHz bandwidth) or an equivalent
- The R&S FSUP26 spectrum analyzer or an equivalent
- A PC with Windows® XP, Windows, Vista (32-bit), or Windows 7 (32-bit)
The SMA coaxial cable is required to connect the RFOUTA+ and RFOUTA− pins of the EVAL-ADF4351EB1Z to CLK0 and CLK0 pins of the ADCLK948/PCBZ.
Functional Block Diagram
For this experiment, the ADCLK948/PCBZ and the EVAL-ADF4351EB1Z are used. The boards are connected via a SMA cable to the ADCLK948/PCBZ, as shown in Figure 1.
Figure 2. ADF4351 Logic Level Measurement Setup
The UG-435 user guide details the installation and use of the EVAL-ADF4351EB1Z evaluation software. UG-435 also contains board setup instructions and the board schematic, layout, and bill of materials. Necessary modifications to the board are the insertion of 100 Ω resistors after the dc blocking capacitor. The resistors are connected to 3.3 V and to GND. This should be done to both the RFOUTA+ and RFOUTA− pins to provide a common-mode voltage of 1.65 V (above the minimum required 1.5 V). This may necessitate scraping off the solder mask near these transmission lines.
The UG-068 user guide contains similar information relevant to the operation of the ADCLK948/PCBZ evaluation board.
In this example, the Rohde & Schwarz RTO1024 oscilloscope is used together with two RT-ZS30 active probes to accurately measure the high speed logic levels.
Install the ADF435x software to PC by doing the following:
- Connect the EVAL-ADF4351EB1Z to the PC, follow the hardware driver instructions as per UG-435.
- Program the ADF4351 PLL as per the screenshot of the ADF435x software (see Figure 3). In this example, an RF frequency of 1 GHz is chosen.
- Using two equal length short SMA cables, connect the RFOUTA+ and RFOUTA− SMA connectors from the EVAL-ADF4351EB1Z board to the CLK0/CLK0 SMA connectors of the ADCLK948/PCBZ board.
- Connect the differential output OUT2/OUT2 of the ADCLK948/PCBZ to the high speed oscilloscope. See Figure 4 for typical waveforms for a 1 GHz output.
Figure 3. ADF4351 Software Settings
Figure 4. ADCLK948 Oscilloscope Output for 1 GHz Logic Signal, Horizontal Axis: 200 ps/DIV, Vertical Axis: 200 mV/DIV
Phase Noise and Jitter Measurement
- Repeat Step 1 to Step 4 from the Logic Level Measurement section.
- Terminate the unused CLK2 output of the ADCLK948/PCBZ with a 50 Ω load (see Figure 5).
- Connect the CLK2 output via a SMA cable to the signal source analyzer (see Figure 5).
- Measure the jitter performance of the signal.
Figure 6 shows the phase noise at the output of the ADF4351, and the rms jitter is 325.7 fs. Figure 7 shows the phase noise at the ADCLK948 output. The rms jitter is 330.4 fs.
The additive jitter of the ADCLK948 can be calculated as √(330.4(sup)2(/sup) − 325.7(sup)2(sup)) = 55.5 fs rms. The specified value from the ADCLK948 data sheet is 75 fs rms.
Figure 5. ADF4351 Phase Noise and Jitter Measurement Setup
Figure 6. ADF4351 Output Phase Noise Measurement Showing 325.7 fs rms Jitter
Figure 7. ADCLK948 Output Phase Noise Measurement Showing 330.4 fs rms Jitter LEARN MORE