ADCLK950
RECOMMENDED FOR NEW DESIGNSTwo Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer
- Part Models
- 2
- 1ku List Price
- Starting From $6.77
Overview
- 2 selectable differential inputs
- 4.8 GHz operating frequency
- 75 fs rms broadband random jitter
- On-chip input terminations
- 3.3 V power supply
The ADCLK950 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs.
The ADCLK950 features 10 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V.
The ADCLK950 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C.
Applications
- Low jitter clock distribution
- Clock and data signal restoration
- Level translation
- Wireless communications
- Wired communications
- Medical and industrial imaging
- ATE and high performance instrumentation
Documentation
Data Sheet 1
User Guide 1
Technical Articles 3
Frequently Asked Question 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADCLK950BCPZ | 40-Lead LFCSP (6mm x 6mm w/ EP) | ||
| ADCLK950BCPZ-REEL7 | 40-Lead LFCSP (6mm x 6mm w/ EP) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Dec 3, 2015 - 15_0255 ADCLK9xx die change |
||
| ADCLK950BCPZ | PRODUCTION | |
| ADCLK950BCPZ-REEL7 | PRODUCTION | |
|
Apr 29, 2015 - 14_0049 Conversion of 6x6mm and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to Amkor Philippines |
||
| ADCLK950BCPZ | PRODUCTION | |
| ADCLK950BCPZ-REEL7 | PRODUCTION | |
This is the most up-to-date revision of the Data Sheet.
Software Resources
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Request a Driver/SoftwareTools & Simulations
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Open ToolADCLK950 IBIS Models 1
Evaluation Kits
Setting Up the Evaluation Board for the ADCLK950