Read other articles in this series:

• 20GHzのダイレクト・サンプリング：全てを1つのナイキスト・ゾーンで—パート1：課題とアプローチ

• 20GHzのダイレクト・サンプリング：全てを1つのナイキスト・ゾーンで -パート2：直交インターリーブ

要約

Leveraging a quadrature error correction (QEC) algorithm can be a differentiating method to expand the Nyquist bandwidth in a software-defined MxFE^® system. Using QEC is critical to expanding the capabilities of a 2-channel ADC receiver used in a quadrature sampling system. However, there are also options to use QEC in a more typical time-interleaving configuration. While either method has distinct merits, a comparison within this discussion will show there is often a superior choice that is application dependent.

Introduction

Part 1 described the interleaving objectives, discussed errors creating interleaving artifacts, and introduced the range of 40 GSPS analog-to-digital conversion (ADC) options using the AD9084. Part 2 presented a direct quadrature sampling option, along with a quadrature correction mechanism in detail. Part 3 presents methods to provide time-interleaving options.

A visual of the embedded digital signal processing (DSP) described in Part 1 is shown in Figure 1. Provisions are included in the clock distribution to internally invert clocks to adjacent ADC channels within the device. The simplest time-interleaving option is to offload all the data from two channels at the full sample rate. Unfortunately, this option requires stitching the data from two channels together within the FPGA or ASIC at the full rate, prior to processing. The power and overhead of this option make it less desirable on its own. An alternate time-interleaving option is one that exploits the data filtering within the embedded DSP, like the quadrature sampling option.

The full data rate power concern creates the need for an option that time interleaves adjacent ADCs, utilizes embedded DSP, and offloads data at reduced rates by leveraging digital down-conversion (DDC). Next, it described how to resolve ADC Nyquist boundaries by exploiting phase information. A unique value shown in these concepts is the option to trade channel count vs. sample rate without increasing the digital data rates, yet still maintaining the use of the programmable embedded DSP capabilities.

Time-Interleaved Slices

Imagine decimating ADC data into even and odd data samples. Each data stream is at half of the sample rate and contains every other sample shifted by one. This is what happens when interleaving ADC slices. Each slice is at half the rate and contains every other sample. A traditional approach is to stitch that data together at the full sample rate. An alternate approach is to utilize the phase information between the two slices that enables resolving Nyquist zones without increasing the digital data rates. Figure 2 introduces the concept of interleaved slices visualized in the frequency domain.

For example, let's look at a 2× time-interleaved ADC:

The sub-ADCs provide the even and odd samples.

If we interpret the sub-ADC signals in the frequency domain, we can relate them back to the desired full-rate signal using equations 4 and 5.

Each sub-ADC signal consists of two aliasing signals from opposite Nyquist zones. The polarity of the aliasing is different for even vs. odd samples. We can exploit this fact to separate the first and second Nyquist zones in postprocessing.

Time Interleaving Followed by FIR Filters

Working with phase information, a method can be created to resolve a slice rate first or second Nyquist signal. Figure 3 illustrates an approach to the solution. Recognize that time delay is a linear phase vs. frequency. Thus, at the ADC output, there is a linear phase vs. input frequency where the slope is based on the time delay of one-half of the slice rate period. The phase difference of both the fundamental and the image frequency is shown in the lower half of Figure 3 compared to the input frequency.

At the output of the ADC, although we see the phase vs. frequency slope, there is not enough information with which to work. If we add a fractional delay of a ½ sample to one of the ADC slices, an important property emerges. The result is that the outputs of the ADCs are in phase if the input frequency is in the first Nyquist and are at a 180° phase difference if the signal is in the second Nyquist. This property enables a method to sum the signals and create a Nyquist zone cancellation method.

This summing method is useful when the signal of interest is not near f_S/2. For signals crossing the f_S/2 boundary, an alternate approach is needed. If a Hilbert transform or a 90° shift is added to the fractional digital filter, then the phase delta is in quadrature at the filter outputs. The quadrature result also has a phase reversal between I and Q at f_S/2 and can be used as quadrature inputs to a complex DDC, making this option analogous to the quadrature sampling option described in Part 2. This can be seen in Figure 4.

Image Correction for Time Interleaving

The previous section discusses several ways that the outputs of two time-interleaved ADCs can be combined to achieve a 2× full-rate signal when assuming that both ADCs are otherwise perfectly matched. However, in practice, there will be gain, phase, and delay mismatch between the ADCs and the branches of the preceding power divider. As with the quadrature sampling technique, the mismatch between ADC paths can be corrected using a half-complex filter structure at the ADC output, or alternatively by summing the outputs of full-complex filters from a pair of DDC channels.

As seen in Figure 5, the time-interleaving system can be modeled as an ideal power splitter feeding two analog signal paths with differing transfer functions, with H₀ (ω) representing the transfer function of the path capturing the even-numbered samples, and H₁ (ω) representing the transfer function of the path capturing the odd-numbered samples. The even and odd signal paths will be referred to as the 0-path and the 1-path.

Like QEC, time-interleaving correction is a relative form of equalization. For example, in Figure 6, the 0-path can be thought of as ideal, and the 1-path can be matched to the 0-path. Therefore, the response of the 1-path can be modeled as the combination of (a) a nominal ½-sample delay, (b) the common response of the 0-path, and (c) a mismatch or delta response of the 1-path relative to the 0-path.

Figure 7 shows the result of stimulating this relative time-interleaving model with a sinusoidal input x(t) = cos (ω₀). The nominal ½-sample delay H_0.5 (ω) and the mismatch response
H_Δ (ω) = A_Δ (ω) e^{(jθΔ (ω))} modify the amplitude and phase of the 1-path signal as shown.

Using simple trigonometric identities, the output of the 1-path can be decomposed into a sum involving delayed cosine terms.

In the absence of mismatch between the 0-path and the 1-path (that is, H_Δ (ω) = 1 ), the ideal outputs of the quadrature sampling configuration can be defined as:

Therefore, for a sinusoidal or other narrowband signal centered at frequency ω₀, the actual outputs can be written in terms of the ideal outputs. The time-interleaving configuration can be viewed as a 2 × 2 linear system that generates time-interleaving error. Time-interleaving error correction is performed by inverting this 2 × 2 linear system to recover the ideal outputs x₀ (t) and x₁ (t), as shown in Figure 8. Note that for the single-tone case depicted in this example, the error correction solution shown in Figure 8 is one of many possible solutions, where the solutions vary by adjusting one filter relative to the other. The error correction solution becomes unique when attempting to simultaneously correct signals in multiple Nyquist zones, but that unique solution is beyond the scope of this article.

This time-interleaving error generation model has similarities with the quadrature sampling error generation model, but there is one significant difference. With a single-tone stimulus, the quadrature sampling error can be modeled and corrected using single-tap real-valued filters. In other words, the correction requires only a gain correction in each of the two real-valued filters. However, time-interleaving correction requires a phase correction and therefore requires a multi-tap crossover filter that spills from the 0-path into the 1-path.

With the topology given, the outputs z₀ [n] and z₁ [n] represent the even-numbered and odd-numbered samples, respectively, of a 2× interleaved signal sampled at twice the rate. The interleaved output z[n] is constructed as follows:

However, as described in previous sections, the ½-sample delay combined with a Hilbert transform can optionally be used to transform the z₀ [n] and z₁ [n] into a quadrature representation. Figure 9 shows the cascade of time-interleaving correction via filters G₀ (ω) and G₁ (ω), and the transformation to quadrature via G_q (ω), resulting in quadrature outputs z[n] = z_i [n] + jz_q [n].

The cascaded filter stages can be merged into a single half-complex filter structure by including the quadrature transformation in the first stage.

Now, with a corrected quadrature output signal, the analysis provided in previous sections can be applied to defer the correction from the ADC output, using the programmable filter (PFILT), to the DDC output, using the complex filter (CFIR).

Measurements are shown in Figure 10 comparing time interleaving vs. quadrature interleaving when using either the PFILT or CFIR for the respective error correction. The results show that the errors are about the same in magnitude for either the time or quadrature interleaving with the CFIR offering improved performance in both cases.

As described in Part 2, the errors after correction with the PFILT are limited by the frequency ripple caused by long transmission lines and impedance mismatch from the RF splitters to the two ADC channels. The PFILT response can approach similar results to the CFIR response after the aforementioned issues are corrected.

Comparison of Interleaving Options

Multiple interleaving options have been described. Next, a comparison of options is warranted. Measurements in Figure 10 show the image rejection performance is about the same for quadrature vs. time interleaving, so the decision about which option is best comes down to other practical application considerations.

Full Rate Offload vs. Embedded DSP

For cases where a full 40 GSPS of data is desired, this is possible and enabled with the latest MxFE solutions. The practical limitation becomes the absorption of the increased data, then calibrating and reforming a 40 GSPS data stream prior to processing. For many cases, it is highly desirable to still monitor a full 20 GHz first Nyquist bandwidth, yet utilize the embedded DSP to reduce the digital backend overhead. The options utilizing the embedded DSP have been the bulk of the descriptions, however offloading full rate data remains a realistic option if desired.

Time vs. Quadrature Interleaving

Quadrature interleaving has two benefits:

• Use of the embedded FFT in complex mode
• The input to the quadrature hybrid can be viewed like a balanced amplifier. Reflections from the ADC will be passed to the termination port providing better broadband impedance matching

The primary drawback of the quadrature sampling is the frequency range limitations of commercially available quadrature hybrids. Commercial parts supporting a 2 GHz to 18 GHz range are available, which is historically a broad bandwidth. If an even larger band is desired, resistive power dividers are readily available that can extend to a lower frequency range.

PFILT vs. CFIR correction

While both the PFILT and the CFIR on the AD9084 support time-interleaving correction, there are pros and cons to each. The PFILT runs at the full ADC sample rate, which allows for a single set of filter coefficients to correct over wide bandwidths and also enables full usage of the embedded DSP functionality. However, the CFIR supports impulse responses of longer duration, which directly translates to improved performance in this application. Table 1 gives a summary of the trade-offs.

Table 1. Comparison of Interleaving Options

Description	Full Rate Offload		Direct Quadrature Sampling		Time Interleaving with Embedded DSP
	Interleave East/West ADC	Interleave Adjacent ADCs	PFILT Correction	CFIR Correction	PFILT Correction	CFIR Correction
40 GSPS ADC Qty.	1	2	2
# JESD Bits	12	8	16 with Decimation
Use of DDCs	No		Yes
Image Errors	Clock Alignment; RF: Gain/Phase/Offset		Quadrature Mismatch: Gain/Phase		Clock Alignment; RF: Gain/Phase/Offset
Complex FFT	No		Yes		No
Benefits	Likely Best Wideband NSD	Simplest Dual Channel 40 GSPS Configuration	Best SWap No FPGA Overhead Digital Flexibility Four CDDCs, Eight FDDCs	Digital Flexibility Two CDDCs Better Calibration	Best SWap No FPGA Overhead Digital Flexibility Four CDDCs, Eight FDDCs Clock Timing Trim	Digital Flexibility Two CDDCs Better Calibration
			Impedance Match with Hybrid Coupler
Drawbacks	Worst SWaP Significant FPGA Effort	Lowest Bit Resolution Significant FPGA Effort		Fewer DDCs Sum in FPGA		Fewer DDCs Sum in FPGA
			Low Freq Limited by Quad Hybrid

Conclusion

In this three-part series, practical methods to enable first Nyquist sampling through 20 GHz with commercially available ADCs have been described. In Part 1, the objectives were introduced and provided an overview of options. In Part 2, direct quadrature sampling was described in detail along with impairments and corrections needed. Part 3 concluded with time-interleaving options and a comparison of options available. Throughout the series, a technical foundation has been provided to show the results achieved in addition to final measurements.

Much effort has gone into maintaining dynamic range and noise performance while simultaneously pushing sample rates. The AD9084 20 GSPS ADCs provide best-in-class performance with input bandwidths through 18 GHz. The performance of those ADCs has remained while interleaving one step further to 40 GSPS and providing options that may be chosen by the user based on application objectives.

Future Work

Future work will be focused primarily on software and firmware upgrades enabling a streamlined integration of the interleaving options in end systems. Evaluation board modification to optimize the RF splitters next to the ADCs will be incorporated.

Acknowledgments

The authors would like to thank the design teams. A combination of the ADC sample rates, input bandwidth, and embedded DSP provided the foundation to develop the concepts discussed. We would also like to thank the long heritage of ADC designers and Analog Devices who paved the decades of design work culminating in 20 GHz first Nyquist, high dynamic range sampling.

References

Ali, Ahmed. High Speed Data Converters. IET, August 2016.

Kester, Walt. The Data Conversion Handbook. Analog Devices, Inc., 200.

Manganaro, Gabriele. Advanced Data Converters. Cambridge University Press, 2012.

著者について

Ian Beavers

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Peter Delos

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Connor Bryant

Connor Bryantは、アナログ・デバイセズのシステム・アプリケーション・エンジニアで、ノースカロライナ州ダーラムにある航空宇宙および防衛ビジネス・ユニットで勤務しています。2023年にアナログ・デバイセズに入社しました。現在は、RFミックスドシグナル・チェーンの設計および解析に焦点を置いています。2022年にNC州立大学からB.S.E.Eの学位、2023年にNC州立大学からM.S.E.Eの学位を取得しています。