- Four M-LVDS transceivers (driver and receiver pairs)
- Switching rate: 250 Mbps (125 MHz)
- Independent pin select for each receiver, two modes:
- Type 1: input hysteresis of 15 mV typical
- Type 2: differential input threshold voltage offset by 100 mV to support open-circuit, short-circuit, and bus idle fail-safe
- Compatible with the TIA/EIA-899 standard for M-LVDS
- Glitch free power-up/power-down on the M-LVDS bus
- Controlled transition times on the driver output
- Common-mode range: −1 V to +3.4 V, allowing communication with ±2 V of ground noise
- Driver outputs high-Z when disabled or powered off
- Independent enable pins for each driver and receiver
- Enhanced ESD protection on bus pins
- ≥±15 kV HBM, air discharge
- ≥±8 kV HBM, contact discharge
- ≥±10 kV IEC 61000-4-2, air discharge
- ≥±8 kV IEC 61000-4-2, contact discharge
- Enhanced ±8 kV HBM ESD protection for all pins, contact discharge
- Operating temperature range: −40°C to +105°C
- Available in 48-lead, 7 mm x 7 mm LFCSP
The ADN4680E comprises four multipoint, low voltage differential signaling (M-LVDS) transceivers (driver and receiver pairs) that can operate at up to 125 MHz, or 250 Mbps nonreturn to zero (NRZ). The driver and receiver of each transceiver are connected in half-duplex configuration, which allows each transceiver to be configured via independent enable pins for either sending or receiving data. Electrostatic discharge (ESD) protection of up to ±15 kV is implemented on the bus pins. The transceivers are optimized for low dynamic power consumption for use in high density applications. The ADN4680E is designed to the TIA/EIA-899 standard for use in M-LVDS networks and complement TIA/EIA-644 LVDS devices with additional multipoint capabilities.
The receivers detect the bus state with a differential input of as little as ±50 mV over a common-mode voltage range of −1 V to +3.4 V. Each receiver can be independently pin selectable as a Type 1 or Type 2 receiver. Type 1 receivers have 15 mV of hysteresis so that slow changing signals or loss of input does not lead to output oscillations. Type 2 receivers exhibit an offset threshold, guaranteeing the output state when the inputs are open (open circuit fail-safe), the bus is idle (bus idle or terminated fail-safe), or when the inputs are hard short circuited.
The device is available in a compact 48-lead, 7 mm × 7 mm LFCSP and operates over a temperature range of −40°C to +105°C.
- Backplane and cable multipoint data transmission
- Multipoint clock distribution
- Low power, high speed alternative to shorter RS-485 links
- Networking and wireless base station infrastructure
- Grid infrastructure and relay protection systems
- Differential extension of SPI networks
The EVAL-ADN4680EEBZ allows quick and easy evaluation of the ADN4680E 250 Mbps, half-duplex, quad multipoint, low voltage differential signaling (M-LVDS) transceivers. The EVALADN4680EEBZ allows the input and output functions of each transceiver to be exercised without the need for external components.
Subminiature A (SMA) connectors provide convenient connections for high speed logic and the M-LVDS bus signals. Screw terminal blocks are available to access power, ground, and digital signals. Jumper options allow control of each transceivers driver and receiver enable pins, each transceivers fail-safe functionality, and the global power-down mode.
The EVAL-ADN4680EEBZ is optimized for high speed signaling. The differential M-LVDS signal traces on the board are routed as a length matched 100 Ω differential pair. The DIx digital input and ROx receiver output are also length matched and routed with a controlled 50 Ω impedance to ground. The EVAL-ADN4680EEBZ features a solid ground and power plane for optimum power integrity.
The EVAL-ADN4680EEBZ has a footprint for the ADN4680E transceivers in a 7 mm × 7 mm, 48-lead LFCSP. For full details on the ADN4680E, see the ADN4680E data sheet, which must be used in conjunction with the user guide when using the EVAL-ADN4680EEBZ.
- Easy evaluation of the ADN4680E 250 Mbps, half-duplex, quad M-LVDS transceivers
- Board layout optimized for high speed signaling
- Matched track lengths on M-LVDS differential pairs with controlled 100 Ω differential impedance
- Matched track lengths on high speed DIx and ROx logic signals with controlled 50 Ω impedance to GND
- SMA jacks for connecting to high speed DIx and ROx logic signals and M-LVDS Ax and Bx signals
- Optional screw terminal connectors for accessing the ROx, REx, DEx, and DIx logic signals
- Power and ground connections through screw terminal blocks
- Jumper-selectable global power down via the ENP pin
- Jumper-selectable driver enable, receiver enable, and fail-safe for each transceiver via the REx, DEx, and FSx pins
- Test points for measuring all signals and multiple ground points to facilitate probing of multiple signals
- 100 Ω termination resistors across Ax and Bx signals to simulate a terminated bus
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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