AN-2573: Completely Isolated, Robust, 4-Channel, Multiplexed Data Acquisition System for Industrial Level Signals

Circuit Function and Benefits

The circuit in Figure 1 is a completely isolated, robust, industrial, 4-channel data acquisition system that provides 16-bit, noise free code resolution and an automatic channel switching rate of up to 42 kSPS. The channel to channel crosstalk at 42 kSPS switching is less than 15 ppm FS (less than −90 dB) because of the unique selection of fast settling components in the multiplexed signal chain.

Figure 1. Functional Block Diagram of 4-Channel Data Acquisition System (Simplified Schematic: All Connections and Decoupling Not Shown).

Figure 1. Functional Block Diagram of 4-Channel Data Acquisition System (Simplified Schematic: All Connections and Decoupling Not Shown).

The circuit acquires and digitizes standard industrial signal levels of ±5 V, ±10 V, 0 V to 10 V, and 0 mA to 20 mA. The input buffers also provide overvoltage protection, thereby eliminating the leakage errors associated with conventional Schottky diode protection circuits.

Applications for the circuit include process control (PLC/DCS modules), battery testing, scientific multichannel instrumentation, and chromatography.

Circuit Description

Signal Path

Four channels of input signals are buffered by the ADA4096-4, a quad, rail-to-rail, input/output op amp featuring overvoltage protection against phase reversal or latch-up for inputs of up to 32 V above or below the ±15 V supply rails, which eliminates the need for additional overvoltage protection circuitry.

The inputs are designed for typical low frequency, industrial signals of ±10 V. The input buffers provide a high impedance to the sources and isolate the inputs from the multiplexer switching transients.

The RC networks on the inputs of the buffers (10 Ω/10 nF) have a bandwidth of 1.6 MHz and provide high frequency noise filtering.

The RC networks on the outputs of the ADA4096-4 (47 Ω/47 nF) isolate the buffers from the multiplexer switching transients. Figure 2 shows an equivalent circuit. The drain capacitor, CD, must be charged by the input voltage before switching to the next channel. There can be as much as 20 V between channels, and a transient current is generated when the multiplexer switches to the next channel.

Figure 2. RC Kickback Isolation Circuit.

Figure 2. RC Kickback Isolation Circuit.

The ADG1204 multiplexer, featuring low drain capacitance (<4 pF), minimizes the kickback charge.

The output of the multiplexer is buffered by an ADA4898-1 op amp to prevent loading errors due to the on resistance of the switches. The ADA4898-1 is unity-gain stable, settles to 0.1% in less than 85 ns, and has only 0.9 nV/√Hz of input voltage noise. The worst-case input signal to the buffer is a ±10 V, 21 kHz square wave when two adjacent channels have full-scale positive and full-scale negative voltages on their respective inputs.

The RC network on the input of the ADA4898-1 (1.8 kΩ/68 pF) has a bandwidth of 1.3 MHz and acts as a wideband noise filter. The time constant of this filter is 122 ns, and the 16-bit settling time is achieved in approximately 1.34 µs (~11 time constants).

The output of the ADA4898-1 buffer drives the AD8475 precision differential funnel amplifier that converts the bipolar, single-ended ±10 V signal into a ±4 V differential signal centered on a common-mode voltage of 2.5 V. With integrated, trimmed, and matched precision resistors configured to a gain of 0.4×, the AD8475 can accept up to ±12.5 V inputs operating on a single 5 V supply. The common-mode voltage is supplied by the REFOUT pin (2.5 V) of the AD7176-2 ADC.

The differential input range of the AD7176-2 is set to ±5 V by the ADR4550 5 V reference.

The AD7176-2 operates both as an ADC and as a multiplexer controller. Enabling the MUX_IO bit causes the GPIO pins in the AD7176-2 to toggle in synchronization with the sequencing and conversion of the ADC channels; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization. The GPIO pins save two control lines to the digital interface that are otherwise needed to control the multiplexer.

A programmable conversion delay from 0 µs to 1 ms can be configured in the AD7176-2. The conversion delay is the delay between each channel change (controlled by the GPIO bits) and the start of a conversion. The delay adjustment allows the multiplexer and conditioning circuits additional settling time.

All the components in the signal path were selected to provide a total minimum settling time that is compatible with the channel switching rate of 42 kSPS. The resulting low frequency crosstalk between channels for full-scale signals is less than −90 dB.

A programmable conversion delay can be inserted between channel switching and start of conversion, thereby allowing maximum settling time for the circuits driving the ADC if further optimization is required.

Digital Isolation and isoPower

The ADuM3471 is a quad channel digital isolator with integrated pulse-width modulation (PWM) controllers and low impedance transformer drivers (X1 and X2). The only additional components required for an isolated dc-to-dc converter are a transformer (Coil-craft KA4976-AL, 1:5 turns ratio, 64 µH primary inductance) and a simple full-wave Schottky diode rectifier (four SD103AW-7-F diodes). The power circuit provides up to 2 W of regulated, isolated power when supplied from a 5 V or 3.3 V input, thereby eliminating the need for a separate isolated dc-to-dc converter.

The iCoupler® chip-scale transformer technology isolates the logic signals, and the integrated transformer driver with isolated secondary side control provides high efficiency for the isolated dc-to-dc converter. The internal oscillator frequency is adjustable from 200 kHz to 1 MHz and is determined by the value of a resistor connected to the OC pin. When the resistor is 100 kΩ, the switching frequency is 500 kHz.

The ADuM3471 regulation is from the positive supply. The feedback for regulation is from a divider network chosen such that the feedback voltage is 1.25 V when the output voltage is 16.76 V. The feedback voltage is compared with the ADuM3471 internal feedback set point of 1.25 V. Regulation is achieved by varying the duty cycle of the PWM signal driving the external transformer.

The ADP7102 LDO regulator regulates the 16.76 V output voltage down to 15 V. The negative unregulated rectified voltage from the transformer is approximately −21 V. The ADP7182 negative regulator is used to provide the regulated −15 V. The regulated ±15 V is then used to power the high voltage components (the ADA4096-4, ADG1204, and ADA4898-1).

Performance Measurement

Noise Free Code Resolution

With the channel input shorted to GND, the circuit measured 17-bit noise free code resolution as shown in Figure 3.

Figure 3. Noise and Resolution at 42 kSPS Switching.

Figure 3. Noise and Resolution at 42 kSPS Switching.

Settling When Multiplexing Between Channels

A 9.6 V source (battery pack) was connected to the system as the input for Channel 1 and Channel 3. A ×9.6 V source was connected to Channel 2 and Channel 4.

The multiplexer was manually set to Channel 1 by setting the GPIO bits to 00, and a histogram of 1000 samples was obtained as shown in Figure 4. The noise free code resolution was better than 16 bits.

Figure 4. Histogram of Single Channel 9.6 V Conversion.

Figure 4. Histogram of Single Channel 9.6 V Conversion.

The multiplexer was then enabled (42 kSPS at 4 µs delay), and a histogram of 1000 samples was obtained for Channel 1 as shown in Figure 5. The noise free code resolution was better than 16 bits.

Figure 5. Histogram of Channel 1 Conversion with Multiplexer Switching Between +9.6 V and −9.6 V at 42 kSPS (4 µs Conversion Delay).

Figure 5. Histogram of Channel 1 Conversion with Multiplexer Switching Between +9.6 V and −9.6 V at 42 kSPS (4 µs Conversion Delay).

Each configuration resulted in better than 16-bit, noise free code resolution, with a slight offset shift in the mean value when multiplexing between channels as shown in Figure 6. The shift is approximately 300 µV (15 ppm FS, or 1 LSB at 16 bits) at 42 kSPS, and can be reduced by adding more conversion delay (configured in the ADC mode register of the AD7176-2) and thereby allowing more settling time before conversions.

Figure 6. Histogram of Channel 1 Conversion with and without Multiplexing.

Figure 6. Histogram of Channel 1 Conversion with and without Multiplexing.

Integral Nonlinearity

Integral nonlinearity (INL) was measured from −11 V to +11 V in 1 V steps using a Fluke 5700 multifunction calibrator and an Agilent 3458 multimeter.

The results are shown in Figure 7, where the endpoint linearity error is calibrated to zero.

Figure 7. INL in ppm of FSR vs. Input Voltage.

Figure 7. INL in ppm of FSR vs. Input Voltage.

With the default values in calibration registers, offset and gain error calculated from −11 V and +11 V were 318 µV and 0.04% FS, respectively, at 25°C.

Table 1 shows the contribution from each device to the offset and gain drift over temperature.

Table 1. Offset and Gain Drift Contributions
Part No. Offset Drift Gain Drift
ADA4096-4 0.4 µV/°C Not applicable
ADA4898-1 0.4 µV/°C Not applicable
AD8475 2.5 µV/°C 1 ppm/°C
AD7176-2 110 nV/°C 0.5 ppm/°C
ADR4550 Not applicable 2 ppm/°C (maximum)
RSS Value 2.56 µV/°C 2.29 ppm/°C
Maximum Value 3.41 µV/°C 3.5 ppm/°C

Common Variations

4 mA to 20 mA Input Configuration

By connecting the voltage inputs to ground with 499 Ω resistors, the circuit operates as a 4-channel, 0 mA to 20 mA, single-ended input. Because the full-scale signal is approximately half of the ADC range, the dynamic range of the system is reduced by 1 bit. The input can be reconfigured for current inputs by making the appropriate external connections to Connector J2.

For example, in the voltage mode for Channel 1, the voltage is applied to Terminal 1 of J2, and the ground to Terminal 3. In the current mode, the current is applied to Terminal 1 and Terminal 2, and the ground to Terminal 3.

Table 2. Connections to J2 for Voltage and Current Input Options
Input Voltage Mode Input Terminals Current Mode Input Terminals
Channel 1 1, 3 (GND) 1 and 2, 3 (GND)
Channel 2 4, 6 (GND) 4 and 5, 6 (GND)
Channel 3 7, 9 (GND) 7 and 8, 9 (GND)
Channel 4 10, 12 (GND) 10 and 11, 12 (GND)

±5 Input Configuration

In the Figure 1 circuit, the 0.4× gain configuration of the AD8475 was chosen. If the 0.8× gain option is chosen, the full-scale range is reduced from ±10 V to ±5 V, yielding twice the sensitivity. The 0.8× gain option also allows full utilization of the ADC input range when using a 4 mA to 20 mA input and a 250 Ω termination resistor.

Achieving Wider Bandwidth

The input bandwidth can be increased by changing the input buffers to the ADA4000-4 and reducing the second stage input filter capacitors. Distortion performance when measuring ac signals also improves significantly.

Scaling the Design to 8 Channels

A second channel consisting of a buffer, multiplexer, and attenuator can be connected to the AN2/AN3 input of the AD7176-2 ADC to achieve 8-channel operation. However, no more than four channels at a time can be automatically sequenced; therefore, running the ADC in single conversion mode and reconfiguring the channel mapping once every four channel conversions is recommended.

The AD7173-8 has a 4-bit GPIO and is capable of sequencing between 16 channels of the external multiplexer. The AD7173-8 is slower (6.21 kSPS channel switching) but consumes less power than the AD7176-2.