How to Optimize a Second-Order Output Filter for an Ultralow Noise µModule Regulator

QUESTION:

Can we further reduce the output switching noise of an ultralow noise μModule® regulator?

How to Optimize a Second-Order Output Filter for an Ultralow Noise µModule Regulator

Answer:

The output noise of an ultralow noise μModule regulator can be reduced by over 90% using a second-order output filter. Proper care must be taken to select the capacitor and inductor components to maintain fast and stable control loop. This design is particularly beneficial for wireless and RF applications, where a fast transient response minimizes system blanking time and maximizes signal processing efficiency. This methodology achieves noise levels comparable to an LDO with the efficiency of a switching regulator.

Introduction

Power consumption for noise sensitive devices is increasingly growing. Applications such as medical ultrasound imaging systems, 5G transceivers, and automatic test equipment (ATE) demand high output current (> 5 A) with a low noise level and high bandwidth in a small PCB area. Due to the high output current demand, the traditional two stage (buck + low dropout (LDO) regulator) solution that was previously used requires more PCB area and incurs more power loss, making it less preferred.

The LTM4702 ultralow noise μModule regulator features Analog Devices’ proprietary Silent Switcher® technology, an ultrafast transient response, and ultralow noise architecture. All these features make it ideal for high current and noisesensitive applications, while still maintaining the high efficiency of a synchronous switching regulator. This solution could eliminate LDO circuitry for many applications, which saves LDO cost (~60%), LDO power loss (4 W and up), and LDO PCB space (2 cm2 + clearance).

For certain applications requiring a very small switching frequency ripple, it is well known that a second-order LC filter can reduce the switching frequency harmonics of the output voltage. However, the design challenge is minimizing the switching ripple while still maintaining a stable control loop with high control loop bandwidth. Often, the control loop becomes unstable after adding an unoptimized LC filter, which causes the output to oscillate. In this article, a simplified loop analysis of the second-order LC filter is first discussed, and then an intuitive design method is given to guide on capacitance distribution and inductance calculation. Lastly, the LTM4702 design example verifies the proposed design method.

Loop Analysis of a Second-Order LC Output Filter Design

In a current-mode buck regulator, the output impedance is the control plant. Figure 1 shows the circuitry of a second-order LC and its typical Bode plot. To maintain accurate DC voltage regulation at load, VOUT remote node B is sensed.

Figure 1. A current-mode buck regulator along with a second-order LC and its typical Bode plot.

The transfer function from VOUT to iLO is:

Equation 1

From the transfer function (Equation 1), the second-order LC filter will introduce double poles with resonant frequency.

Equation 2

From the typical Bode plot shown in Figure 1, there is a sharp 90° phase delay at the resonant frequency. To ensure stability, the resonant frequency should be 4 to 5 times higher than the control loop bandwidth. This is to avoid a 90° phase delay that could cause instability. Also, to provide enough attenuation for the switching frequency ripple, this resonant frequency should be set 4 to 5 times lower than the switching frequency so the LC filter can provide enough filtering. There is a trade-off between attenuation gain at switching frequency and the control loop bandwidth. However, this methodology helps in selecting a resonant frequency with the optimal LC value.

To maintain similar load transient performance, the output impedance should remain consistent before and after adding the LC filter. This means the output capacitance should be roughly the same with or without the LC filter. As a rule of thumb, the capacitance of C2 in Figure 1 can be kept similar to the design without the LC, and C1 can use a much smaller capacitance value so that C1 can dominate the resonant frequency location. Since C1 is much smaller than C2, Equation 2 can simplify into Equation 3:

Equation 3

C1 is recommended to be at least one-tenth the value of C2. Once C1 is chosen, the Lf value can be calculated using the resonant frequency in Equation 3. By checking the availability of real components, the optimum C1 and Lf values can be decided.

Components Selection Considerations

The selections of the capacitor and inductor components are critical in an effective second-order LC filter design. The second-order LC filter needs to provide large enough attenuation at the switching frequency. Since the switching frequency is high (1 MHz to 3 MHz) in an ultralow noise μModule regulator, the inductor and capacitor in the second-order LC require a good high frequency characteristic. The C2 selection requirement is similar to the design without the LC, so it is not discussed here. The C1 and Lf selection criteria is provided below.

  • C1 capacitor selection criteria.

    1. The self-resonant frequency of C1 must be higher than the switching frequency. The impedance of C1 at the switching frequency is the key factor for the second-order LC design. A ceramic capacitor is recommended, and its impedance vs. frequency curve can be referred to determine its self-resonant frequency. Usually, a typical 0603 or 0805 size ceramic capacitor would be ideal, and their self-resonant frequency must be above 3 MHz.
    2. The rms current rating should be high enough to withstand the current flow. Assuming that all the AC ripple goes through C1, the ceramic capacitor should be able to handle a large rms ripple current. The ceramic capacitor’s temperature rise vs. current curve can be referred to determine current capability. For a 0603 size capacitor, ~4 A rms is a good rule of thumb.
  • Lf inductor selection criteria

    1. For output current below 8 A, a ferrite bead is recommended due to its great high frequency characteristic and compact size. Ferrite beads are also helpful to dampen very high frequency spikes.1 For output current above 8 A, or if a large inductance is required, it can be difficult to find a proper ferrite bead, so the traditional shielded inductor is recommended.
    2. Select a ferrite bead/inductor with a sufficient rms current rating (for example, 8 A rms current rating for output current below 8 A). The inductor value is recommended to be less than 10% of the inductor of the μModule device.

Ultralow Noise µModule Design Example

Figure 2 shows a design example of the LTM4702. It features ultralow electromagnetic interference (EMI) emissions and ultralow rms noise. Its switching frequency is adjustable from 300 kHz to 3 MHz. In the design example, it is set to 2 MHz to optimize noise performance for a 12 VIN to 1 VOUT application. According to the proposed LC filter design method, the resonant frequency of a second-order LC is set to 400 kHz to 500 kHz, 4 to 5 times smaller than the switching frequency.

Figure 2. The LTM4702 example circuit and a board photo.

The target control loop bandwidth is 100 kHz, 4 to 5 times smaller than the LC resonant frequency. Two 0603 4.7 μF capacitors are used for C1. Ferrite bead BLE18PS080SH1 is selected as Lf (its size is 0603, as highlighted in Figure 2). Two 1206 100 μF ceramic capacitors are still used as C2. The resonant frequency is 424 kHz.

Equation 4

The noise measurement comparison is shown in Figure 3. At 2 MHz switching frequency, the output switching ripple was 234 μV without the LC and is greatly reduced to 15 μV after adding a 0603 ferrite bead.

Figure 3. Switching noise without the LC (234 μV) vs. with LC (15 μV).

The addition of the second-order LC filter to minimize noise maintains the control loop bandwidth at 100 kHz and fast transient response with recovery below 10 μs, which is confirmed through bench evaluation with and without the LC filter. Recovering within 10 μs allows a negligible blanking time, which is desired in wireless and RF applications. ADI’s LTM4702 resolves the system designer’s challenge of low signal processing efficiency caused by the load transient blanking period.

The load transient waveform shown in Figure 4 verifies fast transient response and recovery within 10 μs after adding the second-order LC filter, similar to the behavior of the design example without this filter.

Figure 4. Load transient results: without LC vs. with LC (recover within 10 μs).

Conclusion

Supporting high current applications with minimal noise while ensuring high efficiency and stability can be challenging. Adding a second-order LC filter can significantly reduce noise but may cause instability if not optimized correctly. To minimize noise without compromising stability, use an optimized second-order LC filter. By carefully selecting the required L and C components based on the switching frequency, control loop bandwidth, and resonant frequency, one can minimize the switching noise while maintaining a fast transient response and high bandwidth.

References

1 Jim Williams. “AN101: Minimizing Switching Regulator Residue in Linear Regulator Outputs.” Linear Technology, July 2005.

Authors

George Qian

Zhijun (George) Qian

George Qian is a senior design manager for power modules with Analog Devices. He is responsible for all LTM80xx products and some LTM46xx/LTM47xx products. He obtained his B.S. degree and M.S. degree from Zhejiang University and his Ph.D. degree from University of Central Florida, all in power electronics. He joined ADI in early 2010.

Jennifer Florence Joseph Benedicto

Jennifer Florence Joseph Benedicto

Jennifer Joseph is a senior design evaluation engineer in the Industrial and Multi-Market Group at Analog Devices working on power modules. She received her bachelor’s degree in electrical and electronics engineering from Jeppiaar Engineering College, India, in 2015 and master’s degree in electrical engineering from Arizona State University in 2018. Following her graduation, Jennifer worked as a product engineer for three years and then started her career at ADI in 2021.