LTC2122

PRODUCTION

Dual14-Bit 170Msps ADC with JESD204B Serial Outputs

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Overview

  • 6.0Gbps JESD204B Interface
  • Only One Output Lane Required for Both ADCs (FS ≤ 150Msps)
  • 70dBFS SNR
  • 90dBFS SFDR
  • Low Power: 751mW Total
  • Single 1.8V Supply
  • Easy to Drive 1.5VP-P Input Range
  • 1.25GHz Full Power Bandwidth S/H
  • Optional Clock Divide by Two
  • Optional Clock Duty Cycle Stabilizer
  • Low Power Sleep and Nap Modes
  • Serial SPI Port for Configuration
  • 48-Lead (7mm × 7mm) QFN Package

The LTC2122 is a 2-channel simultaneous sampling 170Msps 14-bit A/D converter with serial JESD204B outputs. It is designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 70dBFS SNR and 90dBFS spurious free dynamic range (SFDR). The 1.25GHz input bandwidth allows the ADC to under-sample high frequencies.

The JESD204B serial interface simplifies the PCB design by minimizing the number of data lines required. At 170Msps, only two 3.4Gbps output lanes are required. For sample rates up to 150Msps, both ADCs may share the same output lane at up to 6.0Gbps.

The DEVCLK+ and DEVCLK inputs can be driven differentially with sine wave, PECL, or LVDS signals. An optional clock divide-by-two circuit or clock duty cycle stabilizer maintains high performance at full speed for a wide range of clock duty cycles.

Applications

  • Communications
  • Cellular Base Stations
  • Software Defined Radios
  • Medical Imaging
  • High Definition Video
  • Test and Measurement Instrumentation

LTC2122
Dual14-Bit 170Msps ADC with JESD204B Serial Outputs
64k Point 2-Tone FFT, fIN = 71MHz and 69MHz, –7dBFS, 170Msps Product Package 1
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Documentation

Data Sheet

This is the most up-to-date revision of the Data Sheet.

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Software Resources

Evaluation Software 1

KC705 FPGA Source Code for DC1974


Hardware Ecosystem

Parts Product Life Cycle Description
Differential Amplifiers 1
LTC6409 RECOMMENDED FOR NEW DESIGNS 10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver
Digital to Analog Converters (DACs) 1
LTC2000 PRODUCTION 16-/14-/11-Bit 2.5Gsps DACs
Low-Noise Amplifiers (LNAs) & Power Amplifiers 1
LTC6430-15 RECOMMENDED FOR NEW DESIGNS High Linearity Differential RF/IF Amplifier/ADC Driver
Phase-Locked Loop (PLL) Synthesizers 1
LTC6946 LAST TIME BUY Ultralow Noise and Spurious 0.37GHz to 6.39GHz Integer-N Synthesizer with Integrated VCO
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Evaluation Kits

eval board
DC2226A-A

4-Channel 14-Bit 250Msps JESD204B ADC with Clocking [Featuring LTC2123, LTC6951]

Product Details

Demonstration Circuit 2226A-A is a reference design for a four-channel, 250Msps ADC system consisting of two LTC2123, dual 14-bit 250Msps ADCs and a JESD204B Subclass 1 clocking solution based on the LTC6951 Clock Synthesizer with Integrated VCO. Other dash options reserved for future use. No external clock source is required to operate the board; however, the on-board 100MHz reference oscillator may be bypassed, allowing synchronization to other equipment.


Companion Board: Kintex Board

eval board
DC1974A-C

LTC2122 Demo Board | 14-bit, 170Msps Dual ADC with JESD204B Outputs

Product Details

Demonstration circuit 1974 supports the LTC2123 14-bit dual ADC family with JESD204B compliant CML outputs. It was specially designed for applications that require single-ended AC coupled inputs. The DC1974 supports the LTC2123 and LTC2122 with sample rates from 250Msps to 170Msps.


Companion Board: Kintex Board

DC2226A-A
4-Channel 14-Bit 250Msps JESD204B ADC with Clocking [Featuring LTC2123, LTC6951]
DC2226A - Schematic
DC1974A-C
LTC2122 Demo Board | 14-bit, 170Msps Dual ADC with JESD204B Outputs
DC1974A - Schematic

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