DS2154

Enhanced E1 Single Chip Transceiver

Data Sheet (Rev. 2)
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Overview

  • Complete E1(CEPT) PCV-30/ISDN-PRI transceiver
  • Long- and short-haul line eterface for clock/data recovery and waveshaping
  • 32-bit or 128-bit crystalless jitter attenuator
  • Generates line buildouts for both 120Ω and 75Ω lines
  • Frames to FAS, CAS, and CRC4 formats
  • Dual elastic buffers connect to asynchronous backplanes up to 8.192MHz
  • 8-bit parallel control port can be used directly
  • Parallel port can also be muxed or nonmuxed to bus
  • Extracts/inserts CAS signaling
  • Detects/generates remote and AIS alarms
  • Progammable output clocks for Fractional E1, H0, and H12
  • Independent transmit/receive functions
  • Full access to both Si and Sa bits aligned with CRC multiframe
  • Four testing loopbacks
  • Large error counter for bipolar and code, CRC4 code/word, FAS, and E-bits
  • Pin-compatible with DS2152 T1 Transceiver
  • Operating ranges:
    • 5V, low-power CMOS
    • 0°C to +70°C (DS2154L)
    • -40°C to +85°C (DS2154LN)

The DS2154 is a second-generation line interface unit for E1 lines. It is pin- and software-compatible with the first-generation DS2153Q and function- and pin-compatible with the DS2152, its T1 counterpart. The DS2154 retains all features of the DS2153Q adding crystalless jitter attenuation, additional hardware signaling, a full HDLC controller for the FDL layer with 16-byte buffers, and the option for nonmultiplexed bus operation.

The DS2154 meets E1 specifications, including ETS 300 011, 300 233, 300 166, TBR 12, and TBR 13 and ITU G.703, G.704, G.706, G.823, and I.431.

Through the parallel port, the user can quickly access the 8-bit internal registers and configure the DS2154 to the application under processor control.
DS2154
Enhanced E1 Single Chip Transceiver
DS2154: Pin Configuration
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Documentation

Data Sheet 1

Reliability Data 1

Application Note 3

Design Note 21

Technical Articles 3

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