Overview
Features and Benefits
- 100 MHz (10 ns) SIMD SHARC DSP core
- 600 MFLOPS (32-bit floating-point data), 600 MOPS (32-bit fixed-point data)
- Code-compatible with all SHARC DSPs
- Supports IEEE-compatible 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point math
- Single-cycle instruction execution, including SIMD operations in both computational units
- One Mbit on-chip dual-ported SRAM
- 2.4 Gbyte/sec on-chip data bandwidth
- 14 zero-overhead DMA channels
- Four synchronous serial ports with I2S support
- Serial ports support 128 channels TDM frames with selection of companding on a per channel basis
- Integrated support for SDRAM and SBSRAM external memories
- Support for single-cycle, 100 MHz instruction execution from x48-bit wide external memories
Product Details
The ADSP-21161 SHARC® DSP is the newest member of the Super Harvard Architecture (SHARC) family of programmable DSPs. Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs - more than three times the performance for comparable models at about the same price. Its road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10 GFLOPS and beyond.
"This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications and should help others reconsider applications they couldn’t do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."
The ADSP-21161 DSP is the second member of the SHARC DSP family of 32-bit floating-point programmable DSPs to be based on a SIMD core architecture that is optimized for digital signal processing performance. Like all SHARCs, the ADSP-21161 is code-compatible with all other members of the family and supports both fixed- and floating-point data types. The ADSP-21161 lowers the price for SIMD SHARC DSP performance and is an outstanding DSP solution for many price-sensitive applications.
State-of-the-Art Development Tools
The ADSP-21161, like all SHARC processors, is supported by a complete set of software and hardware development tools. The VisualDSP++® tool set offered by Analog Devices includes an optimizing C/C++ compiler, integrated development environment (IDE), assembler, linker, splitter and cycle accurate simulator that support both C and assembly debugging. Emulation support is JTAG-based and ADI offers USB, PCI, and Ethernet based emulators.
SHARC DSP Roadmap
There are two code-compatible paths that the SHARC DSP roadmap will follow. One optimized for high-performance multiprocessing systems and the other for price/performance. Performance is the key for multiprocessing applications and this is the reason that ADI will offer 10 GFLOP SHARC DSPs in the future. On-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 Mbit) using newly developed technologies.
Industry leading price/performance will be the driver on the other path of the roadmap. In the future, these SHARC DSPs will offer an increase in performance to 1200 MFLOPs while decreasing price to as low as $5.00. This is required to support new technologies that demand substantial signal processing performance at consumer price points.
Product Categories
Product Lifecycle
Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
Documentation & Resources
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EE-112: Class Implementation in Analog C++11/14/2016
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EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2)2/14/2015
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• EE-356: Associated Files
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EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009
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• EE-332: Code example
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EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev. 1)5/8/2009
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• EE-340: Code example
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EE-163: ADSP-21161N SHARC On-chip SDRAM Controller (Rev. 2)4/7/2008
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EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008
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• EE-323: Associated Code
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EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007
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EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007
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EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007
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• EE-175: Associated Files
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EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007
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EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007
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• EE-84: Code Example (Rev 2, 2/2007)
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EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007
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• EE-223: Code Example (Rev 2, 02/2007)
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006
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EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)11/15/2006
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EE-278: Interfacing NAND Flash Memory with ADSP-21161 SHARC® Processors (Rev. 1)11/22/2005
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• EE-278 Software Code
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EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005
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• EE-270 Software Code
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EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005
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• EE-267 Software Code
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005
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EE-259: Interfacing AD7865 Parallel ADCs to ADSP-21161 SHARC® Processors (Rev. 1)12/17/2004
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• EE-259 Software Code
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EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004
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• EE-202 Software Code
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EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)7/19/2004
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• EE-241 Software Code
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EE-219: Connecting Character LCD Panels to ADSP-21262 SHARC® DSPs (Rev. 1)12/30/2003
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• EE-219 Software Code
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EE-212: Connecting the AD74111 Mono Audio Codec Evaluation Board to the ADSP-21161N SHARC® EZ-KIT™ Lite Board10/24/2003
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• EE-212 Software Code
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EE-209: Asynchronous Host Interface on ADSP-21161N SHARC® Processors (Rev. 2)10/8/2003
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EE-199: Link Port Booting the ADSP-21161 SHARC® DSP9/10/2003
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• EE-199 Software Code
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EE-194: Connecting the AD1836A Evaluation Board to the ADSP-21161N SHARC EZ-KIT Lite™6/5/2003
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• EE-194 Software Code
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EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003
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• EE-191 Software Code
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EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003
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• EE-177: Code Example (Rev 3, 01/2007)
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EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002
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EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs12/16/2002
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EE-180: Using Code Overlays from ROM on the ADSP-21161N EZ-KIT Lite12/8/2002
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• EE-180 Software Code
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TN: Considerations for Selecting a DSP Processor ADSP-21161 vs TMS360C6711/129/26/2002
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TN: Interfacing the ADSP-21161 SIMD SHARC DSP to the AD1836 (24-bit/96 kHz) Multichannel Codec9/26/2002
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EE-138: Recommended Handling of Unused ADSP-21161 Pins9/18/2002
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EE-136: Using the Programmable I/O FLAGS and IOFLAG register on the ADSP-211619/18/2002
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• EE-136 Software Code
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EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family9/18/2002
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EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™9/18/2002
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• EE-132 Software Code
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EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002
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EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002
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• EE-69: Code Example (Rev 2, 01/2007)
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EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000
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EE-151: Implementing Software Data Overlays for the ADSP-21161 Using the EZ-KIT1/1/2000
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• EE-151 Software Code
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EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999
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• EE-104 Software Code
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SHARC Processor Family9/21/2010
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EZ-KIT Lite for Analog Devices ADSP-21161N SHARC Processor4/2/2008
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Sensing, Analyzing, and Acting in the First Moments of an Earthquake1/1/2001 Analog Dialogue
Software & Systems Requirements
Software & Tools Anomaly
Software Development Tools
CrossCore® Embedded Studio
CCES is a world-class integrated development environment (IDE) for the ADI Blackfin®, SHARC® and Arm® processor families.
Tools & Simulations
Design Tool
BSDL Model File
Designing with BGA
Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages
ADSP-21161: 225 ball PBGA and MBGA Packages Silicon (Rev. 1.1)
[BSDL Revision] 1.9, [Date] 05/28/02
IBIS Model
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| ADSP-21161NCCAZ100 | Material Declaration | Reliability Data | 225-Ball CSPBGA (17mm x 17mm) | |
| ADSP-21161NKCAZ100 | Material Declaration | Reliability Data | 225-Ball CSPBGA (17mm x 17mm) | |
| ADSP-21161NYCAZ110 | Material Declaration | Reliability Data | 225-Ball CSPBGA (17mm x 17mm) | |
| Wafer Fabrication Data |
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