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  5. ADSP-21161N


Features and Benefits

  • 100 MHz (10 ns) SIMD SHARC DSP core
  • 600 MFLOPS (32-bit floating-point data), 600 MOPS (32-bit fixed-point data)
  • Code-compatible with all SHARC DSPs
  • Supports IEEE-compatible 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point math
  • Single-cycle instruction execution, including SIMD operations in both computational units
  • One Mbit on-chip dual-ported SRAM
  • 2.4 Gbyte/sec on-chip data bandwidth
  • 14 zero-overhead DMA channels
  • Four synchronous serial ports with I2S support
  • Serial ports support 128 channels TDM frames with selection of companding on a per channel basis
  • Integrated support for SDRAM and SBSRAM external memories
  • Support for single-cycle, 100 MHz instruction execution from x48-bit wide external memories

Product Details

The ADSP-21161 SHARC® DSP is the newest member of the Super Harvard Architecture (SHARC) family of programmable DSPs. Capable of 600 million math operations per second (MFLOPs), the ADSP-21161 sets a new level of performance for low-cost SHARC DSPs - more than three times the performance for comparable models at about the same price. Its road map includes a cost-effective path to 1200 MFLOPS for $5 per unit and a performance-driven path to 10 GFLOPS and beyond.

"This newest edition to the SHARC family will open more possibilities for designers to design-in high performance digital signal processing into client-side applications and should help others reconsider applications they couldn’t do before with a single chip," said Will Strauss, president of Forward Concepts. "Analog Devices will certainly maintain customer loyalty with this road map."

The ADSP-21161 DSP is the second member of the SHARC DSP family of 32-bit floating-point programmable DSPs to be based on a SIMD core architecture that is optimized for digital signal processing performance. Like all SHARCs, the ADSP-21161 is code-compatible with all other members of the family and supports both fixed- and floating-point data types. The ADSP-21161 lowers the price for SIMD SHARC DSP performance and is an outstanding DSP solution for many price-sensitive applications.

State-of-the-Art Development Tools

The ADSP-21161, like all SHARC processors, is supported by a complete set of software and hardware development tools. The VisualDSP++® tool set offered by Analog Devices includes an optimizing C/C++ compiler, integrated development environment (IDE), assembler, linker, splitter and cycle accurate simulator that support both C and assembly debugging. Emulation support is JTAG-based and ADI offers USB, PCI, and Ethernet based emulators.


There are two code-compatible paths that the SHARC DSP roadmap will follow. One optimized for high-performance multiprocessing systems and the other for price/performance. Performance is the key for multiprocessing applications and this is the reason that ADI will offer 10 GFLOP SHARC DSPs in the future. On-chip memory sizes will be balanced to match this performance with memories increasing to unprecedented levels (64 Mbit) using newly developed technologies.

Industry leading price/performance will be the driver on the other path of the roadmap. In the future, these SHARC DSPs will offer an increase in performance to 1200 MFLOPs while decreasing price to as low as $5.00. This is required to support new technologies that demand substantial signal processing performance at consumer price points.


Product Lifecycle icon-recommended Production

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

Evaluation Kits (1)

Documentation & Resources

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  • Data Sheet (1)
  • Application Note (42)
  • User Guide (1)
  • Processor Manual (3)
  • Integrated Circuit Anomaly (1)
  • Legacy Emulator Manual (2)
  • Product Highlight (2)
  • Product Selection Guide (1)
  • Technical Article (1)
  • Application Note

    Software & Systems Requirements

    Software & Tools Anomaly

    Software Development Tools

    Tools & Simulations

    BSDL Model File

    Designing with BGA

    Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages

    IBIS Model

    ADSP-21161N R1.1 IBIS Datafile BGA Package

    [IBIS Ver]2.1,[File Rev]2.3,[Date] 10/31/01

    Design Resources

    ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.

    Part Number Material Declaration Reliability Data Pin/Package Drawing CAD Symbols, Footprints & 3D Models
    ADSP-21161NCCAZ100 Material Declaration Reliability Data 225-Ball CSPBGA (17mm x 17mm)
    ADSP-21161NKCAZ100 Material Declaration Reliability Data 225-Ball CSPBGA (17mm x 17mm)
    ADSP-21161NYCAZ110 Material Declaration Reliability Data 225-Ball CSPBGA (17mm x 17mm)
    Wafer Fabrication Data

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