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ADL5303: 160 dB Range, 100 pA to 10 mA Logarithmic Converter Data Sheet (Rev. D)1/24/2013PDF419 K
Overview
Features and Benefits
- Optimized for fiber optic photodiode interfacing
- 8 full decades of range
- Law conformance: 0.1 dB from 1 nA to 1 mA
- Single-supply operation: 3.0 V to 5.5 V
- Complete and temperature stable
- Accurate laser trimmed scaling
- Logarithmic slope of 10 mV/dB (at the VLOG pin)
- Basic logarithmic intercept at 100 pA
- Easy adjustment of slope and intercept
- Output bandwidth of 10 MHz, 15 V/μs slew rate
- Miniature 16-lead package (LFCSP)
- Low power: ~4.5 mA quiescent current (enabled)
Product Details
The ADL5303 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems and offers a large dynamic range in a versatile and easily used form. Wide measurement range and accuracy are achieved using proprietary design and precise laser trimming. The ADL5303 requires only a single positive supply, VPS, of 5 V. When using low supply voltages, the log slope can be altered to fit the available span. Low quiescent current and chip disable facilitate use in battery-operated applications.
The input current, IPD, flows in the collector of an optimally scaled NPN transistor, connected in a feedback path around a low offset JFET amplifier. The current summing input node operates at a constant voltage, independent of current, with a default value of 0.5 V; this may be adjusted over a wide range. An adaptive biasing scheme is provided for reducing photo-diode dark current at very low light input levels. The VPDB pin applies approximately 0.1 V reverse bias across the photodiode for IPD = 100 pA, rising linearly to 2.0 V of reverse bias at IPD = 10 mA to improve response time at higher power levels. The input pin INPT is flanked by the VSUM guard pins that track the voltage at the summing node. Connecting the exposed pad of the device to the VSUM pins provides a continuous guard to minimize leakage into the INPT pin.
The default value of the logarithmic slope at the VLOG output is set by an internal 5 kΩ resistor. Logarithmic slope can be lowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. The addition of a capacitor at the VLOG pin provides a simple low-pass filter. The intermediate voltage, VLOG, is buffered in an output stage that can swing to within about 100 mV of ground and the positive supply, VPS, and provides a peak current drive capacity of ±20 mA. An on-board 2 V reference is provided to facilitate the repositioning of the intercept. The incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. At IPD =1 nA, the bandwidth of the ADL5303 is approximately 2 kHz increasing in proportion to IPD up to a maximum value of 10 MHz.
APPLICATIONS
- High accuracy optical power measurement
- Wide range baseband log compression
- Versatile detector for APC loops
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
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| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| ADL5303ACPZ-R2 | Material Declaration | Reliability Data | 16-Lead LFCSP (3mm x 3mm w/ EP) | |
| ADL5303ACPZ-R7 | Material Declaration | Reliability Data | 16-Lead LFCSP (3mm x 3mm w/ EP) | |
| ADL5303ACPZ-RL | Material Declaration | Reliability Data | 16-Lead LFCSP (3mm x 3mm w/ EP) | |
| Wafer Fabrication Data |
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