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Features
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The AD9763/AD9765/AD9767 have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9763/AD9765/AD9767 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature.
The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 380 mW of power.
Product Highlights
- The AD9763/AD9765/AD9767 are members of a pin- compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
- Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information.
- Matching. Gain matching is typically 0.1% of full scale, and offset error is better than 0.02%.
- Low Power. Complete CMOS dual DAC function operates on 380 mW from a 3.3 V to 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods.
- On-Chip Voltage Reference. The AD9763/AD9765/AD9767 each include a 1.20 V temperature-compensated band gap voltage reference.
- Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767 each feature a flexible dual-port interface, allowing dual or interleaved input data.
Applications
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AD9767
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Documentation
Data Sheet 1
User Guide 1
Application Note 5
AN-595: Understanding Pin Compatibility in the TxDAC® Line of High Speed D/A Converters (Rev.0)
AN-320A: CMOS Multiplying DACs and Op Amps Combine to Build Programmable Gain Amplifier, Part 1
AN-137: A Digitally Programmable Gain and Attenuation Amplifier Design
AN-237: Choosing DACs for Direct Digital Synthesis
AN-912: Driving a Center-Tapped Transformer with a Balanced Current-Output DAC
3rd Party Solutions 3
Solutions Bulletin & Brochure 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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| AD9767ASTZ |
48-Lead LQFP (7mm x 7mm)
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| AD9767ASTZRL |
48-Lead LQFP (7mm x 7mm)
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- AD9767ASTZ
- Pin/Package Drawing
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48-Lead LQFP (7mm x 7mm)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
- AD9767ASTZRL
- Pin/Package Drawing
-
48-Lead LQFP (7mm x 7mm)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
Filter by Model
Part Models
Product Lifecycle
PCN
Dec 7, 2016
- 16_0033
Assembly Relocation to Stats ChipPAC Jiangyin and Test Transfer to Stats ChipPAC Singapore of Select QFP Products
AD9767ASTZ
PRODUCTION
AD9767ASTZRL
PRODUCTION
Jan 5, 2009
- 07_0077
Certification of STATSChipPAC Shanghai, China and AMKOR Philippines as additional sources for Assembly & Test of QFP Packages
AD9767ASTZ
PRODUCTION
AD9767ASTZRL
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Dec 7, 2016
- 16_0033
Assembly Relocation to Stats ChipPAC Jiangyin and Test Transfer to Stats ChipPAC Singapore of Select QFP Products
AD9767ASTZ
PRODUCTION
AD9767ASTZRL
PRODUCTION
Jan 5, 2009
- 07_0077
Certification of STATSChipPAC Shanghai, China and AMKOR Philippines as additional sources for Assembly & Test of QFP Packages
AD9767ASTZ
PRODUCTION
AD9767ASTZRL
PRODUCTION
Software & Part Ecosystem
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
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I/Q Modulators1 |
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PRODUCTION |
700 MHz TO 2.7 GHz Direct Up-Conversion Quadrature Modulator |
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Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 2
EVAL-AD9767
AD9765/63/09 Evaluation Board
Resources
SDP-H1
High Speed Controller Board
Features and Benefits
- Xilinx® Spartan 6
- 1 x FMC Low Pin Count ( LPC) connector
- LVDS and single ended LVCMOS signaling
- DDR2
- JTAG header
- Blackfin processor ADSP-BF527
- 1 x small Footprint 120 pin connector
- Configurable Peripheral Interfaces SPI, SPORT, I2C, GPIO, Asynchronous Parallel, PPI, Timers
- USB 2.0 interface to the PC
Product Detail
The SDP-H1 is a high speed controller board for the System Demonstration Platform (SDP). The SDP-H1 has a Xilinx® Spartan 6 and an ADSP-BF527 processor with connectivity to the PC through a USB 2.0 high speed port. Controller boards allow for the configuration and capture of data on daughter boards from the PC via USB.
The SDP-H1 has a FMC low pin count ( LPC) connector with full differential LVDS and singled ended LVCMOS support. It also has the 120 pin connector, found on the SDP-B which exposes the Blackfin processors peripherals. This connector provides a configurable Serial, Parallel I2C and SPI and GPIO communications lines to the attached daughter board. The PC side software application for controlling the attached daughter board is provided with each of the daughter product evaluation boards or Circuits from the Lab reference Circuits.
The System Demonstration Platform is a collection of controller boards, interposer boards, and daughter boards, used for easy, low cost evaluation of ADI components and reference circuits. For a general overview of the entire platform visit the System Demonstration Platform homepage www.analog.com/sdp
See the full list of compatible Product Evaluation Boards and Circuits from the Lab Reference Circuit Boards that require the SDP-B. All SDP-S compatible daughter boards can be used with the SDP-B.
Resources
Tools & Simulations 1
IBIS Model 3
IBIS Model
