Features and Benefits

  • DAC update rate: up to 5.7 GSPS
  • Direct RF synthesis at 2.85 GSPS data rate
    • DC to 1.425 GHz in baseband mode
    • DC to 1.0 GHz in 2× interpolation mode
    • 1.425 GHz to 4.2 GHz in Mix-Mode
  • Bypassable 2× interpolation
  • Excellent dynamic performance
  • Supports DOCSIS 3.0 wideband ACLR/harmonic performance
    • 8 QAM carriers: ACLR > 65 dBc
  • Industry-leading single/multicarrier IF or RF synthesis
    • 4-carrier W-CDMA ACLR at 2457.6 MSPS
      • fOUT = 900 MHz, ACLR = 71 dBc (baseband mode)
      • fOUT = 2100 MHz, ACLR = 68 dBc (Mix-Mode)
      • fOUT = 2700 MHz, ACLR = 67 dBc (Mix-Mode)
  • Dual-port LVDS and DHSTL data interface
    • Up to 1.425 GSPS operation
    • Source synchronous DDR clocking with parity bit
  • Low power: 1.0 W at 2.85 GSPS (1.3 W at 5.7 GSPS

Product Details

The AD9119/AD9129 are high performance, 11-/14-bit RF digital-to-analog converters (DACs) supporting data rates up to 2.85 GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode™ or 2× interpolation. The high dynamic range and bandwidth enable multicarrier generation up to 4.2 GHz.

In baseband mode, wide bandwidth capability combines with high dynamic range to support from 1 to 158 contiguous carriers for CATV infrastructure applications. A choice of two optional 2× interpolation filters is available to simplify the postreconstruction filter by effectively increasing the DAC update rate by a factor of 2. In Mix-Mode operation, the AD9119/AD9129 can reconstruct RF carriers in the second and third Nyquist zone while still maintaining exceptional dynamic range up to 4.2 GHz. The high performance NMOS DAC core features a quad-switch architecture that enables industry-leading direct RF synthesis performance with minimal loss in output power. The output current can be programmed over a range of 9.5 mA to 34.4 mA.

The AD9119/AD9129 include several features that may further simplify system integration. A dual-port, source synchronous LVDS interface simplifies the data interface to a host FPGA/ASIC. A differential frame/parity bit is also included to monitor the integrity of the interface. On-chip delay locked loops (DLLs) optimize timing between different clock domains.

A serial peripheral interface (SPI) configures the AD9119/ AD9129 and monitors the status of readback registers. The AD9119/AD9129 are manufactured on a 0.18 μm CMOS process and operates from +1.8 V and −1.5 V supplies. It is supplied in a 160-ball chip scale package ball grid array.

Product Highlights

  1. High dynamic range and signal reconstruction bandwidth support RF signal synthesis of up to 4.2 GHz.
  2. Dual-port interface with double data rate (DDR) LVDS data receivers supports 2850 MSPS maximum conversion rate.
  3. Manufactured on a CMOS process; a proprietary switching technique enhances dynamic performance.


  • Broadband communications systems
    • CMTS/VOD
    • Wireless infrastructure: W-CDMA, LTE, point-to-point
  • Instrumentation, automatic test equipment (ATE)
  • Radar, jammers

Product Lifecycle icon-recommended Recommended for New Designs

This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

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Product Recommendations

AD9129 Companion Parts

Recommended PLL with Integrated VCO

  • For high performance and lower cost: ADF4350.
  • For high performance and widest input frequency: ADF4351.

Recommended Clock Generation Device

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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