AD4632-20
PRE-RELEASE20-Bit, 2MSPS/500kSPS Dual-Channel SAR ADCs
- Part Models
- 2
- 1ku List Price
- Starting From $22.09
Overview
- High performance
- Throughput: 2MSPS (AD4630-20) or 500kSPS (AD4632-20) per channel maximum
- INL: ±0.8ppm typical from −40°C to +125°C
- SNR: 105.7dB typical
- THD: −127dB typical
- NSD: −166dBFS/Hz typical
- Low power
- 15mW per channel at 2MSPS
- 5mW per channel at 500kSPS
- 1.5mW per channel at 10kSPS
- Easy Drive features reduce system complexity
- Low 0.6μA input current for DC inputs at 2MSPS
- Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF
- Flexible external reference voltage range: 4.096V to 5V
- Accurate integrated reference buffer with 2μF bypass capacitor
- Programmable block averaging filter with up to 216 decimation
- Extended sample resolution to 30 bits
- Overrange and synchronization bits
- Flexi-SPI digital interface
- 1, 2, or 4 SDO lanes per channel allows slower SCK
- Echo clock mode simplifies use of digital isolator
- Compatible with 1.2V to 1.8V logic
- 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint
The AD4630-20/AD4632-20 are 2-channel, simultaneous sampling, Easy Drive™, 2MSPS or 500kSPS successive approximation register (SAR) analog-to-digital converters (ADCs). With a guaranteed typical ±0.8ppm INL and no missing codes at 20 bits, the AD4630-20/AD4632-20 achieve unparalleled precision from −40°C to +125°C. Figure 1 shows the functional architecture of the AD4630-20/AD4632-20.
A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4630-20/ AD4632-20 offer a typical dynamic range of 106dB when using a 5V reference. The low noise floor enables signal chains, which require less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 153dB. The wide differential input and common-mode ranges allow inputs to use the full voltage reference (±VREF) range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front end (AFE) components compatible with the AD4630-20/AD4632-20. Both single-ended and differential signals are supported.
The versatile Flexi-SPI serial-peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10MHz while operating at a sample rate of 2MSPS or 500kSPS. Echo clock and ADC host clock modes relax the timing requirements and simplify the use of digital isolators.
The 64-ball chip-scale package ball grid array (CSP_BGA) of the AD4630-20/AD4632-20 integrates all critical power supply and reference bypass capacitors, which reduce the footprint and system component count, and lessening sensitivity to board layout.
APPLICATIONS
- Automatic test equipment
- Digital control loops
- Medical instrumentation
- Seismology
- Semiconductor manufacturing
- Scientific instrumentation
Documentation
Data Sheet 1
User Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD4632-20BBCZ | CSP_BGA | ||
| AD4632-20BBCZ-RL | CSP_BGA |
This is the most up-to-date revision of the Data Sheet.
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