Phase Sync in Digital Phased Arrays Through Direct RF Sampling—Part 1: The Basics

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Figure 1

   

摘要

An all-digital beamforming radar system is dependent on the degree to which the transmit and receive channels are synchronized. Since the phases to all channels are applied in the digital domain, there arises a need to establish a known and repeatable phase difference between all the channels. This article presents a methodology to synchronize multiple modular circuit boards, equipped with high speed data converters, to build a concept of a scalable digital beamforming system. This work involves achieving phase repeatability over power cycles by syncing multiple wideband digitizer integrated circuits (ICs), which is a four-transmit and four-receive data converter with high on-chip digital signal processing (DSP) capabilities.

Introduction

Early antenna array systems deployed mechanical systems to rotate the antenna in order to point the beam to the desired direction. With the advent of phased array systems, the steering of the beam has been done electronically by applying phase offsets to individual antenna elements. In an all-digital beamforming system, the radio frequency (RF) signal from each antenna element is directly digitized by an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). These ADCs and DACs generally have sampling rates and analog usable bandwidths of up to a few GHz. This enables direct digitization of the L/S/C/X and Ku bands.

Scanning the entire volume of area with a single beam lowers the scan rate. An element-level digital approach is adopted that provides a faster scan rate and through multiple beams in the area of interest. Each of these subarrays has individual gain and phase control for each element. Unlike the hybrid or the analog beamforming technique, each antenna element is digitized by a distinct channel of a high speed data converter.¹ Present-day high speed converters have multiple ADCs and DACs integrated and hence offer better channel density.

With advancements in the technology of high speed data converters (HSx), a lot of digital signal processing (DSP) has been embedded into a single integrated circuit (IC).² This relaxes the resource and power consumption on the field-programmable gate array (FPGA) used in the subarray module. DSP components, such as decimation and interpolation blocks, allow the baseband sampling rates to be low (a few tens of MHz to a few GHz) and the final sampling rate to be high (a few GHz). This allows the FPGA to operate at lower sampling rates. There are integrated numerically controlled oscillators (NCOs) that allow frequency upconversion and downconversion through the IC itself. The usage of such ICs guarantees good noise performance³ as well as simplification of the RF signal chain, as it eliminates the need for multiple stages of frequency upconversion and downconversion.

Large all-element digital phased arrays depend on the phase relationship between all channels. This makes the entire radar system dependent on a calibration that establishes a known phase offset between the channels. The RF channels will emanate from different high speed converter ICs housed on different boards. This work proposes a method to ease the system-level calibration by achieving a known phase relationship between the channels of multiple AD9081s, thus allowing a lookup table (LUT)⁴ to be populated with these precalibrated phase values.

The degree of repeatability has been demonstrated through oscilloscope statistics in the following sections.

Clock Generation, Distribution, and Synchronization

Radar systems that aim to achieve synchronization rely on how well clocks are synchronized. In addition, multiple boards must receive a reference from the same reference source; hence, a clock tree must be synthesized to enable this. This work involves the use of the HMC7044 on the AD9081 evaluation boards and the AD-SYNCHRONA14-EBZ, which also has the HMC7044 inside the module.

The HMC7044 is a clock generator and distribution IC that has a two phase-locked loop (PLL) architecture. The first PLL (PLL1) acts as a jitter cleaner, meaning it allows a noisy reference to lock to a cleaner voltage-controlled crystal oscillator that sits locally on the individual boards. In this work, the AD-SYNCHRONA14-EBZ distributes references to the AD9081 evaluation boards. Usually, the loop filter of PLL1 has a very narrow bandwidth, which allows the cleaner VCXO that sits locally on the board to dominate the clock noise performance at lower offsets. The architecture of the HMC7044 is shown in Figure 1.

Capable of distributing 14 outputs, the HMC7044 can be used to distribute device clocks to the wideband digitizers as well as the necessary FPGA and system references (SYSREFs). Each of the 14 outputs has individual delay controls that help align clocks by compensating for any phase discrepancies arising due to trace mismatches. Synchronization between these 14 outputs can be carried out by a serial peripheral interface (SPI) based reseed command, but since this work involves syncing multiple of such ICs, the SYNC pin was used to distribute an aligned synchronization pulse to the HMC7044s. In a successful capture of this sync pulse, the outputs of multiple clock distribution ICs should be aligned to each other. The clock tree setup with the AD9081 evaluation boards and the AD-SYNCHRONA14-EBZ will be described in Part 2 of this series.

An Overview of the Wideband Digitizer Architecture and Sync Overview

This work aims to achieve a repeatable phase offset between multiple AD9081s that fall under the family of high speed digitizers. There is an immense amount of DSP that has been embedded within the digitizer, as shown in Figure 2. The ADCs and DACs within the digitizer can sample at maximum rates of 4 GSPS and 12 GSPS, respectively. Programmable filters (PFILT) are integrated along the receive path, where the user can program custom coefficients to implement a digital finite impulse response (FIR) filter. The digital upconverters (DUCs) and downconverters (DDCs) help in dividing or multiplying the data rates to and from the FPGA. The DDC and DUC blocks also include the NCOs for frequency translation.

The analog ADC supports a bandwidth of up to 8 GHz. The baseband interface is over the standard JESD (JEDEC Electrical Standard for Data) protocol and both JESD204B and JESD204C versions are supported.

The MxFE^® family provides the option to either feed the high frequency sampling clock (12 GHz) directly or supply a low frequency clock of a few hundred MHz and use the internal PLL to generate the 12 GHz sampling clock. In this work, the latter has been implemented. The clock receiver pins remain the same, and the user can control the mode of clocking through the application programming interface (API) in the firmware.

The DSP blocks relevant to this work are the internal PLL, the NCOs, and the sync logic. The sync logic works in a two-fold step. The first is the one-shot sync that aligns the baseband clocks and other clocks within the IC, and the second consists of the alignment of the NCOs for the different digitizers. The one-shot sync is dependent on the capture of an externally fed SYSREF clock signal. In this work, the SYSREF signal used was a continuous signal, but an N-pulse and a gapped periodic signal are also supported. The one-shot sync aligns the internal local multiframe clock (LMFC)/local extended multiblock clock (LEMC) to the external continuous SYSREF. The AD9081 provides a register that can be read back to confirm the completion of the one-shot sync.⁵

In the case of an AD9081, once the bit describing the status of the one-shot sync is read back as high, the phase offset of the LMFC and the external continuous SYSREF can be measured to determine how well they are aligned. For this, the digitizer IC features a register that stores the phase offset between the LMFC and the SYSREF in units of DAC sampling clock cycles. In this work, the DAC sampling clock was set to 12 GHz. A zero read back from the phase registers implies that the LMFC is, indeed, aligned to SYSREF coming from the clock distribution IC, the core of the clocking system on the AD9081 development boards used.

The second step is to align the NCOs. This step can be understood as the synchronization of local oscillators (LOs) in the analog RF domain. There are two ways to do this, namely resetting the NCOs directly with an external SYSREF or using a general-purpose input/output (GPIO) based system. This work used the leader-follower-based sync, where one of the boards acts as the leader that triggers the synchronization on both the leader and the follower boards and uses a GPIO for alignment between platforms. There is a firmware and hardware description language (HDL) dependency to make this happen, which will be described in detail in Part 2. The API prepares both the digitizers for triggering the NCO sync and the NCOs reset at the same time on the next rising edge of the LMFC on both the boards. The one-shot sync, followed by the leader-follower NCO sync, forms the basis of syncing multiple digitizers. Additionally, the NCOs allow phase control within the range of –180° to +180°, and this is exposed through the APIs.

To offer added flexibility, the digitizer offers multiple options to initiate the NCO reset after a specific GPIO has been captured: the external SYSREF, the LMFC rising edge, or the LMFC falling edge. The API is configured to reset the NCOs at the next LMFC rising edge after the GPIO pin is driven high by default, but this work uses the SYSREF signal for triggering the reset action.

The above method of NCO sync is applicable when there is a provision of a connection of a GPIO pin between the leader and the follower boards. If there isn’t one, another method has also been evaluated where all the boards are set as followers, and the baseband logic device issues a GPIO high on both the digitizers. During the initial phases of the project, the codes were made to wait for keyboard inputs to allow for the GPIOs triggering the reset to be set manually. Once the concept was proven to be working, this was automated through the HDL and firmware, waiting for the GPIOs to be triggered.

Since the clocks being fed to the digitizer IC also need to have a repeatable phase relationship, there is also a need to sync the clock distribution ICs, on both the leader and follower boards, that generate the SYSREFs and the device clocks for the digitizers. The clock distribution ICs have been synced through a complementary metal oxide semiconductor (CMOS) pulse into the SYNC pins. In the setup, the AD-SYNCHRONA14-EBZ clock controller generates phase-aligned references and CMOS sync pulses to the HMC7044s on the leader and follower AD9081 evaluation boards.

The methodologies described in the previous section also remain applicable if the AD9081s are on the same board.

Conclusion

Part 1 discussed the internal blocks of the clock distribution and the digitizer IC, the overall procedure that should be employed to achieve a clock sync, and thereafter, sync multiple AD9081 digitizers. Part 2 will discuss the procedure with the API codebase for the AD9081, HMC7044, and the FPGA HDL. Part 2 will present the actual hardware implementation and the results of phase repeatability, which have been achieved between the two AD9081 evaluation boards.

References

¹Connor Pope, Hong Tang, Bowen Zheng, and Hualiang Zhang.“Phased Array Systems—Design Considerations and System Demonstration.” 2024 IEEE International Symposium on Phased Array Systems and Technology (ARRAY), October 2024.

²W. Michael Jones, Stephen Pancrazio, Bryce Readyhough, and John Majewski.“A 0.1-20 GHz Digitizer SOM Useful for Phased Array Applications in a Standardized Form Factor.” 2024 IEEE International Symposium on Phased Array Systems and Technology (ARRAY), October 2024.

³ Caleb Fulton, Mark Yeary, Daniel Thompson, John Lake, and Adam Mitchell.“Digital Phased Arrays: Challenges and Opportunities.” Proceedings of the IEEE, Vol. 104, 2016.

⁴ Michael Jones, Michael Hennerich, and Peter Delos.“Power-Up Phase Determinism Using Multichip Synchronization Features in Integrated Wideband DACs and ADCs.” Analog Devices, Inc., October 2020.

⁵ System Development User Guide for the AD9081 and AD9082 Direct RF Sampling Transceivers.

Analog Devices, Inc., May 2023.

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