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ADF4196:  Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer

Product Details

Product Status:Recommended for New Designs

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications.

The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.

Applications

  • GSM/EDGE base stations
  • PHS base stations
  • Pulsed Doppler Radar
  • Instrumentation and test equipment
  • Beam-forming/phased array systems

FEATURES and BENEFITS

  • Fast settling, fractional-N
    PLL architecture
  • Single PLL replaces ping-pong synthesizers
  • Frequency hop across GSM band in 5 μs with phase settled within 20 μs
  • 1 degree rms phase error at
    4 GHz RF output
  • Digitally programmable output phase
  • Digitally programmable output phase
  • RF input range up to 6 GHz
  • 3-wire serial interface
  • On-chip, low noise differential amplifier
  • Phase noise figure of merit: –216 dBc/Hz
  • Loop filter design possible using ADIsimPLL

Functional Block Diagram for ADF4196

Documentation

Title Content Type File Type
ADF4196: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer Data Sheet (Rev C, 01/2013) (pdf, 2801 kB) Data Sheets PDF
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers  (pdf, 207 kB) Application Notes PDF
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Webcasts WEBCAST
UG-536: Evaluating the ADF4193 and ADF4196 Frequency Synthesizers for Phase-Locked Loops  (pdf, 443 kB) User Guides PDF
UG-476: PLL Software Installation Guide  (pdf, 520 kB) User Guides PDF
New Analog Devices’ PLL Synthesizers Deliver Utmost Flexibility and Phase Noise Performance (05 Jan 2012) Press Releases HTML
PLLs/Synthesizers Product Highlight  (pdf, 269 kB) Overview PDF
PLL Synthesizers/VCOs - Overview  (pdf, 510 kB) Overview PDF
RF Source Booklet  (pdf, 815 kB)
RF IC Product Overview - Version O (11/2012)
Overview PDF
Clock and Timing ICs  (pdf, 4970 kB) Overview PDF
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

Design Tools,Models,Drivers & Software

Title Content Type File Type
ADIsimRF
ADI’s ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain, including cascaded gain, noise figure, IP3, P1dB, and total power consumption.
ADIsim Design/Simulation Tools HTML
ADIsimPLL™- Version 3.43
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
ADIsim Design/Simulation Tools HTML
ADF4196 Evaluation Board Software  (zip, 1165 kB) Evaluation Software ZIP

Evaluation Kits & Symbols & Footprints

Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.

SampleSample & Buy

Price, packaging, availability

ADF4196 Model Options
Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

ADF4196 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
Purchase/Sample
EV-ADF4196SD1Z Status: Contact ADI Evaluation Board (No VCO or Loop Filter) $141.00 Yes -
EVAL-SDP-CS1Z Status: Production SDP-S Controller Board - Interface to EV-ADF4196SD1Z (also required) $49.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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