AD9540

RECOMMENDED FOR NEW DESIGNS

Low Jitter, DDS-based Clock Generator and Synthesizer

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Overview

  • Excellent intrinsic jitter performance
  • 200 MHz phase frequency detector inputs
  • 655 MHz programmable input dividers for the phase frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
  • Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
  • 8 programmable phase/frequency profiles
  • 400 MSPS internal DDS clock speed
  • 48-bit frequency tuning word resolution
  • 14-bit programmable phase offset
  • 1.8 V supply for device operation
  • 3.3 V supply for I/O, CML driver, and charge pump output
  • Software controlled power-down
  • 48-lead LFCSP package
  • Programmable charge pump current (up to 4 mA)
  • Dual-mode PLL lock detect
  • 655 MHz CML-mode PECL-compliant output driver

The AD9540 is Analog Devices’ first dedicated clocking product specifically designed to support the extremely stringent clocking requirements of the highest performance data converters. The device features high performance PLL (phase-locked loop) circuitry, including a flexible 200 MHz phase frequency detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CML-mode, PECL-compliant output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported.

Extremely fine tuning resolution (steps less than 2.33 µHz) is another feature supported by this device. Information is loaded into the AD9540 via a serial I/O port that has a device write speed of 25 Mbps. The AD9540 frequency divider block can also be programmed to support a spread spectrum mode of operation.

The AD9540 is specified to operate over the extended automotive range of −40°C to +85°C.

Applications

  • Clocking high performance data converters
  • Base station clocking applications
  • Network (SONET/SDH) clocking
  • Gigabit Ethernet (GbE) clocking
  • Instrumentation clocking circuits
  • Agile LO frequency synthesis
  • Automotive radar
  • FM chirp source for radar and scanning systems
  • Test and measurement equipment
  • Acousto-optic device drivers

AD9540
Low Jitter, DDS-based Clock Generator and Synthesizer
AD9540 Functional Block Diagram AD9540 Pin Configuration
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Documentation

Data Sheet 1

Application Note 22

Technical Articles 24

Product Highlight 1

Frequently Asked Question 1

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Software Resources

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Hardware Ecosystem

Parts Product Life Cycle Description
Comparators 1
LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter
Phase-Locked Loop (PLL) Synthesizers 1
ADF4002 RECOMMENDED FOR NEW DESIGNS Phase Detector / PLL Frequency Synthesizer
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Tools & Simulations

ADIsimCLK Design and Evaluation Software

ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

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Evaluation Kits

EVAL-AD9540

OBSOLETE: AD9540 Evaluation Board

Product Details

This evaluation board is obsolete and no longer recommended.

This page contains evaluation board documentation for evaluating the AD9540.

EVAL-AD9540
OBSOLETE: AD9540 Evaluation Board

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