AD9228: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates ...More
To drive this ADC in DC-coupled applications, we suggest AD8139 or ADA4938-1. To drive this ADC in AC-coupled applications, we suggest AD8351. To select a VGA to use with this ADC, please visit our VGA selection table.
Technical Article: Complete Analog Front End (AFE) for Advanced Ultrasound Equipment
AD9228: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Product Description
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.
Product Highlights
- Small Footprint. Four ADCs are contained in a small, space-saving package.
- Low power of 119 mW/channel at 65 MSPS.
- Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation.
- User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.
- Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9259 (14-bit).
Applications
Data Sheet, Rev. B, 7/07
- Data Sheet Rev B, 07/2007 (pdf 2015kB)
- (About Data Sheets)
Features
- 4 ADCs integrated into 1 package
- 119 mW ADC power per channel at 65 MSPS
- SNR = 70 dB (to Nyquist)
- ENOB = 11.3 bits
- SFDR = 82 dBc (to Nyquist)
- Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical) - Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3) - Data and frame clock outputs
- 315 MHz full-power analog bandwidth
- 2 V p-p input voltage range
- 1.8 V supply operation
- Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Diagrams
- Enlarge
- Other Diagrams
- Symbols and Footprints
Functional Block Diagram for AD9228
Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
Other Diagrams for AD9228
Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
AD9228 Pin Configuration
Functional Block Diagram for AD9228
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| Part# | Res | Throughput Rate | # of Inputs | Operating Pwr Diss |
|---|---|---|---|---|
| AD9228-65 | 12 | 65MSPS | 4 | 510mW |
| AD9627-80 | 12 | 80MSPS | 2 | 490mW |
| AD9219-65 | 10 | 65MSPS | 4 | 408mW |
| AD9230-170 | 12 | 170MSPS | 1 | 407mW |
| AD9236 | 12 | 80MSPS | 1 | 411mW |
| AD9233-105 | 12 | 105MSPS | 1 | 350mW |
| AD9226 | 12 | 65MSPS |
