| Title |
Content Type |
File Type |
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AD9540: 655 MHz Low Jitter Clock Generator Data Sheet (Rev A, 02/2006) (pdf, 839 kB)
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Data Sheets |
PDF
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AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus
(pdf, 112 kB)
|
Application Notes |
PDF
|
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AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal
(pdf, 221 kB)
|
Application Notes |
PDF
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AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)
(pdf, 170 kB)
|
Application Notes |
PDF
|
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AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 (Rev. A, 6/07)
(pdf, 284 kB)
|
Application Notes |
PDF
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AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance
(pdf, 313 kB)
|
Application Notes |
PDF
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AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)
(pdf, 439 kB)
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Application Notes |
PDF
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AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers
(pdf, 207 kB)
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Application Notes |
PDF
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AN-769: Generating Multiple Clock Outputs from the AD9540
(pdf, 0)
|
Application Notes |
PDF
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AN-823: Direct Digital Synthesizers in Clocking Applications Time
(pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems
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Application Notes |
PDF
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AN-851: A WiMax Double Downconversion IF Sampling Receiver Design
(pdf, 262 kB)
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Application Notes |
PDF
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AN-847: Measuring a Grounded Impedance Profile Using the AD5933
(pdf, 294 kB)
|
Application Notes |
PDF
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AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
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Application Notes |
PDF
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter
(pdf, 291 kB)
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Application Notes |
PDF
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AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
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Application Notes |
PDF
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AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers
(pdf, 527 kB)
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Application Notes |
PDF
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AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR
(pdf, 138 kB)
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Application Notes |
PDF
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AN-621: Programming the AD9832/AD9835
(pdf, 202 kB)
This application note details how to program 5 MHz on the output of the AD9832/AD9835 parts. The frequency
register,defer register,and command sequence are explained in detail.
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Application Notes |
PDF
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AN-342: Analog Signal-Handling for High Speed and Accuracy.
(pdf, 468 kB)
Signal handling techniques for optimizing DAC and ADC performance.
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Application Notes |
PDF
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AN-280: Mixed Signal Circuit Technologies
(pdf, 2101 kB)
Considers problems which arise when reality (& Murphy) intervene in a design which otherwise seems satisfactory in terms of theory and modeling.
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Application Notes |
PDF
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AN-557: An Experimenter's Project:
(pdf, 368 kB)
Incorporating the AD9850 Complete DDS Device as a Digital LO Function in an Amateur Radio Transceiver
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Application Notes |
PDF
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AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850
(pdf, 101 kB)
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Application Notes |
PDF
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AN-237: Choosing DACs for Direct Digital Synthesis
(pdf, 1156 kB)
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Application Notes |
PDF
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AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer
(pdf, 37 kB)
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Application Notes |
PDF
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AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers
(pdf, 116 kB)
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Application Notes |
PDF
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AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS
(pdf, 49 kB)
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Application Notes |
PDF
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Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
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Webcasts |
WEBCAST
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Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
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Webcasts |
WEBCAST
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Network Clock: How To Achieve Maximum System Up Time
In this in-depth Webcast, our clock expert will explore the technical implications of this very real system scenario, and discuss the incorporation of seamless reference switchover and holdover technology that maintains a stable, low-jitter, system clock during periods of switchover, and complete reference loss, conditions.
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Webcasts |
WEBCAST
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Ask The Application Engineer—33: All About Direct Digital Synthesis
(Analog Dialogue, Vol. 38, August 2004)
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Analog Dialogue |
HTML
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Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
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Technical Articles |
HTML
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Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou
(Electronic Design, April 27, 2006)
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Technical Articles |
HTML
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Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
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Technical Articles |
HTML
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Low-power direct digital synthesizer cores enable high level of integration
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Technical Articles |
HTML
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Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
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Technical Articles |
HTML
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ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
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Technical Articles |
HTML
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DDS Device Provides Amplitude Modulation
by Mary McCarthy, Analog Devices, Inc.
(EDN, September 2, 1999)
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Technical Articles |
HTML
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Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters
(pdf, 63 kB)
Revolutionize your radio architectures
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Technical Articles |
PDF
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Digital Up/Down Converters: VersaCOMM™ White Paper
(pdf, 97 kB)
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Technical Articles |
PDF
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Basics of Designing a Digital Radio Receiver (Radio 101)
(pdf, 77 kB)
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Technical Articles |
PDF
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The Year of the Waveform Generator
(Test & Measurement World, 12/1/2005)
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Technical Articles |
HTML
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Synchronized Synthesizers Aid Multichannel Systems
by David Brandon and John Kornblum, Analog Devices, Inc. (Microwaves & RF, 9/2005)
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Technical Articles |
HTML
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DDS Applications
by Eva Murphy and Colm Slattery, Analog Devices, Inc. (EETimes, 9/26/2005)
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Technical Articles |
HTML
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DDS IC Initiates Synchronized Signals
(Microwaves & RF Cover Story, July 2005)
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Technical Articles |
HTML
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DDS Simplifies Polar Modulation
By Ken Gentile, Analog Devices ... Basic modulation mathematics and DDS (direct digital synthesis) provide designers with an all-digital technique for generating polar-encoded carrier signals. (EDN, 8/5/2004)
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Technical Articles |
HTML
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Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement
by Colm Slattery, Analog Devices (EDN, 12/17/2004)
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Technical Articles |
HTML
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Integrated DDS Chip Takes Steps To 2.7 GHz
This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump. (ED Online, April 2004)
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Technical Articles |
HTML
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Two DDS ICs Implement Amplitude-shift Keying
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 12/25/2003)
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Technical Articles |
HTML
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DDS Circuit Generates Precise PWM Waveforms
by Colm Slattery, Analog Devices, Inc. (EDN, 10/2/2003)
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Technical Articles |
HTML
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DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 2/5/2004)
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Technical Articles |
HTML
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Simple Circuit Controls Stepper Motors
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 1/8/04)
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Technical Articles |
HTML
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Digital Potentiometers Vary Amplitude In DDS Devices
(PDF)
(Electronic Design, Ideas for Design, 5/29/2000)
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Technical Articles |
PDF
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AD9858: Flexible Integrated Synthesizer For Wireless
(htm)
... The most important feature of the AD9858 is its ability to change frequency in less than 5 ns, meaning that there is virtually no application left where you will need to go the expense of switching between two separate synthesizers. (AnalogZone, RF/IF Zone Products for the Week of 9/23/2002)
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Technical Articles |
HTM
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DDS Device Produces Sawtooth Waveform
Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control. (EDN Design Idea, 7/10/2003)
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Technical Articles |
HTML
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400-MSample DDSs Run On Only +1.8 VDC
... This line of highly integrated DDS ICs features on-board RAM and
crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms. (Microwaves & RF Cover Story, 12/2002)
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Technical Articles |
HTML
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DDS Tackles BaseStations Head On
... This High-Performance, Low-Power Integrated Hybrid Synthesizer Flaunts A 10-b Digital-To-Analog Converter
That Operates At Up To 1 GSample/s.
(Wireless Systems Design, September 2002)
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Technical Articles |
HTML
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Video Portables and Cameras Get HDMI Outputs
By Doug Bartow, Analog Devices, Inc.
|
Technical Articles |
HTML
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Clock Requirements For Data Converters
(Electronic Design, 2/2005)
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Technical Articles |
HTML
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DDS Design
By David Brandon, Analog Devices, Inc.
Direct digital synthesizers are known for their highly accurate digital tuning, low noise figure, and phase-continuous frequency-hopping capabilities, which make them more attractive than alternative analog frequency-synthesis solutions.
(EDN, 5/13/2004)
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Technical Articles |
HTML
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Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
|
Technical Documentation |
PDF
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Free Direct Digital Synthesis IC Evaluation Tool
(Control Engineering, 9/14/2006)
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Product Reviews |
HTML
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Where Analog Really Meets Digital
(EE Time, 8/29/2005)
|
Product Reviews |
HTML
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On-Line Evaluation Tool Simplifies Implementing DDS Semiconductors
(eeProductCenter, 8/16/2006)
|
Product Reviews |
HTML
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Circuit Simulation Tool Simplifies Clock Designs
(eeProductCenter, 8/23/2005)
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Product Reviews |
HTML
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Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04)
|
Product Reviews |
HTML
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Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005)
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Product Reviews |
HTML
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Low Jitter Clock Generator for Data Converters
... Analog Devices' first dedicated clocking product supporting the stringent needs of high performance data converters. (AVNET Technology Review, November 2004,
Vol. 10, Issue 11)
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Product Reviews |
HTML
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RF Source Booklet
(pdf, 815 kB)
RF IC Product Overview - Version O (11/2012)
|
Overview |
PDF
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Expanding Family of Integrated Clock ICs
|
Overview |
HTML
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Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks
(pdf, 64 kB)
|
Overview |
PDF
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Optical and High Speed Networking
(pdf, 2236 kB)
Analog Devices’ optical and high speed networking ICs solve a depth
and breadth of challenges faced by today’s designers of datacom
and telecom systems, optical modules, and subsystems. Analog
Devices products address a wide range of networking applications
from O/E/O conversion, clock recovery, and backplane transmission
to monitoring and control of optical power, power management, and
clock generation and distribution.
|
Overview |
PDF
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Reset your thinking about clocks.
(pdf, 153 kB)
... In precision timing, analog is everywhere.
|
Overview |
PDF
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Clock and Timing ICs
(pdf, 4970 kB)
|
Overview |
PDF
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My evaluation board is not working; the software is reporting a USB Communication Error. I verified that the evaluation board is connected to the PC and powered. What else can I check?
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FAQs/RAQs |
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Why do I see reference spurs?
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FAQs/RAQs |
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Why is my phase noise shape changing when I change the PLL settings?
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FAQs/RAQs |
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Why doesn't the PLL make my reference input and the clock outputs line up?
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FAQs/RAQs |
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How do I optimize my PLL loop for the best phase noise and/or jitter?
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FAQs/RAQs |
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My loop is not locking. How do I debug this?
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FAQs/RAQs |
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How long does it take for the PLL to lock?
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FAQs/RAQs |
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Help! My PLL came unlocked over temperature.
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FAQs/RAQs |
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How do I choose between active and passive filter in PLL loop?
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FAQs/RAQs |
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Should I reference the passive filter to ground? or supply?
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FAQs/RAQs |
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How do the PLLs in the AD951x parts compare to other ADI PLLs?
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FAQs/RAQs |
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How does the clock clean-up function of the AD951x parts work?
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FAQs/RAQs |
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Why do I want to run a fast PFD frequency?
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FAQs/RAQs |
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Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins?
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FAQs/RAQs |
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Why can't I use a bandpass filter for my loop filter?
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FAQs/RAQs |
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Should I tie my loop filter to ground or PLL supply?
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FAQs/RAQs |
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The loop filter was working great until I changed the divide ratio in PLL. What happened?
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FAQs/RAQs |
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How do I use a VCO with a supply greater than 5V?
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FAQs/RAQs |
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What suppliers do you recommend for VCO/VCXOs?
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FAQs/RAQs |
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Do VCXOs have better phase noise and jitter performance than VCOs?
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FAQs/RAQs |
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How do I know which VCO will work best with the AD9510?
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FAQs/RAQs |
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Is there an advantage to running a higher VCO frequency than the output frequency?
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FAQs/RAQs |
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How do I determine if a VCO is good enough for my purpose?
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FAQs/RAQs |
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Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip?
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FAQs/RAQs |
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Do different divide ratios cause variations in jitter?
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FAQs/RAQs |
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I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips?
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FAQs/RAQs |
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Do divide ratios change the propagation delay?
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FAQs/RAQs |
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I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset?
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FAQs/RAQs |
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On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter?
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FAQs/RAQs |
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Why doesn't the mini-divider support the divide ratio I want?
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FAQs/RAQs |
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I want to use the variable delay adjust, but the jitter is too high. What can I do?
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FAQs/RAQs |
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I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on?
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FAQs/RAQs |
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What is the difference between the coarse phase adjust and the fine delay adjust?
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What is the fine delay adjust which is available on certain LVDS/CMOS outputs?
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Does the fine delay adjust affect the jitter?
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Why is the fine delay adjust not available on all the outputs?
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Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11?
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FAQs/RAQs |
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Will the AD9510 work without a reference input signal?
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FAQs/RAQs |
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What are the best clock sources for a distribution-only design?
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I am not using the CLK1 input on the AD9510. Can I just leave it floating?
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FAQs/RAQs |
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How good does my input signal need to be?
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FAQs/RAQs |
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I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked.
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FAQs/RAQs |
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Can I shift the threshold on clocks for single-ended inputs?
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FAQs/RAQs |
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The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510?
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FAQs/RAQs |
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Will differential or single-ended inputs/outputs improve my jitter?
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Why should I use differential rather than single-ended?
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FAQs/RAQs |
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How do I feed a single-ended signal into a differential input?
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Why do you recommend AC coupling, rather than DC coupling, at the clock inputs?
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FAQs/RAQs |
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Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts?
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Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs?
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On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate?
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I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong?
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Can I use the 951X clocks to drive a mixer (RF LO)?
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My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications?
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I have an input present at the clock input, but I'm not seeing an output?
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What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away?
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What clock frequency comes out of the AD9510 outputs when you first apply power to the device?
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Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF)
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I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz?
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What should I do with unused channels on the AD9510?
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Can I tri-state the AD9510 outputs?
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On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
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What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter?
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Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output?
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What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs?
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Does the AD9510 support 2.5V PECL?
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How much bandwidth is required to process a PECL or LVDS output?
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If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output?
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If I change the level of PECL output, does it affect the jitter?
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What is the best way to terminate LVPECL outputs to get lowest jitter?
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Is it okay to AC-couple PECL or LVDS outputs?
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What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs?
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What is the proper termination (value and location) for outputs?
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Are outputs short-circuit protected?
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Are the CMOS drivers on the clock devices complementary?
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Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)?
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I have pulled SYNCB low, but I still have output from a channel. Why?
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Why can I not get the same output amplitude or rise and fall times as stated in your datasheet?
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The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work?
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May I use the AD9540 for spread spectrum clocking?
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Can I get two clock outputs from the AD9540?
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What's the advantage of a DDS-based clock generator?
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Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter?
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I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications?
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On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong?
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How do you determine the bandwidth over which phase noise is integrated to obtain jitter?
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Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification?
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How do harmonic spurs in the output spectrum affect jitter (random or deterministic)?
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When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed?
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How do you specify jitter?
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How do I use the clock part for jitter clean-up?
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If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers?
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Does jitter vary with different clock frequencies? How about phase noise?
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I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts?
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Do you guarantee performance shown in ADIsimCLK?
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Who do I contact for technical support on ADIsimCLK?
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Should I use the minimum charge pump current settings in order to minimize power?
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Can I run CMOS outputs at 5V?
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Can I use different power supply voltages for the PECL output drivers?
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Is .01 uF sufficient for power supply pin bypass?
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My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power?
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Why don't you spec psrr and cmrr in the datasheet?
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How do I get two AD951x (with PLL) to synchronize to the same reference input edge?
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I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN?
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How do I synchronize multiple clock devices?
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What happens if I run the part in an ambient environment which exceeds 85°C?
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How can I determine the die temperature of your device?
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My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND?
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What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package?
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Does Analog Devices offer a list of manufacturers of oscillators for DDS devices?
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Where can I find some good background material on direct digital synthesis?
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