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AD9540:  Low Jitter, DDS-based Clock Generator and Synthesizer

Product Details

Product Status:Recommended for New Designs

The AD9540 supports a variety of functions including signal synthesis and low jitter clock generation useful in a wide variety of applications. The device features high performance PLL circuitry including a flexible 200 MHz Phase Frequency Detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CML mode (PECL compatible) output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. An onboard 400 MSPS DDS provides extremely fine tuning resolution and phase programmability. Information is loaded into the AD9540 via a serial I/O port which has a device write speed of 25Mbit/sec. The AD9540 frequency divider block can also be programmed to support a spread spectrum clocking mode.

The AD9540 is specified to operate over the extended automotive range of -40°C to +85°C.

Applications

  • Clocking high performance data converters
  • Basestation clocking applications
  • Network (SONET/SDH) clocking
  • Gigabit Ethernet (GbE) clocking
  • Instrumentation clocking circuits

FEATURES and BENEFITS

  • Intrinsic Jitter performance < 500 fs
  • Synthesizes signals to 2.7 GHz
  • Generates clock signals to 655 MHz
  • 25 Mbit/sec write speed Serial I/O Control
  • 200 MHz Phase Frequency Detector Inputs
  • 400 MSPS DDS onboard
    Programmable edge delay w/ 93 fs resolution
    Frequency resolution <2.33 µHz
  • 655 MHz Programmable Input Dividers for the Phase Frequency Detector (÷M,N) {M,N =1..16} (bypassable)
  • 8 Programmable internal clock rates
  • 1.8 V Supply for device operation
    3.3 V Supply for I/O, CML Driver & Charge Pump Output
  • Software controlled power-down
  • 48-lead LFCSP package
  • Programmable charge pump current (up to 4 mA)

Functional Block Diagram for AD9540

Of Note ...

Two evaluation boards are available for the AD9540:
AD9540-VCO/PCB: Evaluation board with 1.6 GHz VCO and correlating loop filter
AD9540/PCB: Evaluation Board with no VCO and unpopulated loop filter

An Overview of the Clock Distribution/Generation Family is available.

Documentation

Title Content Type File Type
AD9540:  655 MHz Low Jitter Clock Generator Data Sheet (Rev A, 02/2006) (pdf, 839 kB) Data Sheets PDF
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus  (pdf, 112 kB) Application Notes PDF
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal  (pdf, 221 kB) Application Notes PDF
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)  (pdf, 170 kB) Application Notes PDF
AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 (Rev. A, 6/07)  (pdf, 284 kB) Application Notes PDF
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance  (pdf, 313 kB) Application Notes PDF
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)  (pdf, 439 kB) Application Notes PDF
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers  (pdf, 207 kB) Application Notes PDF
AN-769: Generating Multiple Clock Outputs from the AD9540  (pdf, 0) Application Notes PDF
AN-823: Direct Digital Synthesizers in Clocking Applications Time  (pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems
Application Notes PDF
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design  (pdf, 262 kB) Application Notes PDF
AN-847: Measuring a Grounded Impedance Profile Using the AD5933  (pdf, 294 kB) Application Notes PDF
AN-345: Grounding for Low-and-High-Frequency Circuits  (pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
Application Notes PDF
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) Application Notes PDF
AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
Application Notes PDF
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers  (pdf, 527 kB) Application Notes PDF
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR  (pdf, 138 kB) Application Notes PDF
AN-621: Programming the AD9832/AD9835  (pdf, 202 kB)
This application note details how to program 5 MHz on the output of the AD9832/AD9835 parts. The frequency register,defer register,and command sequence are explained in detail.
Application Notes PDF
AN-342: Analog Signal-Handling for High Speed and Accuracy.  (pdf, 468 kB)
Signal handling techniques for optimizing DAC and ADC performance.
Application Notes PDF
AN-280: Mixed Signal Circuit Technologies  (pdf, 2101 kB)
Considers problems which arise when reality (& Murphy) intervene in a design which otherwise seems satisfactory in terms of theory and modeling.
Application Notes PDF
AN-557: An Experimenter's Project:  (pdf, 368 kB)
Incorporating the AD9850 Complete DDS Device as a Digital LO Function in an Amateur Radio Transceiver
Application Notes PDF
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD9850  (pdf, 101 kB) Application Notes PDF
AN-237: Choosing DACs for Direct Digital Synthesis  (pdf, 1156 kB) Application Notes PDF
AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer  (pdf, 37 kB) Application Notes PDF
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers  (pdf, 116 kB) Application Notes PDF
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS  (pdf, 49 kB) Application Notes PDF
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Webcasts WEBCAST
Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
Webcasts WEBCAST
Network Clock: How To Achieve Maximum System Up Time
In this in-depth Webcast, our clock expert will explore the technical implications of this very real system scenario, and discuss the incorporation of seamless reference switchover and holdover technology that maintains a stable, low-jitter, system clock during periods of switchover, and complete reference loss, conditions.
Webcasts WEBCAST
Ask The Application Engineer—33: All About Direct Digital Synthesis
(Analog Dialogue, Vol. 38, August 2004)
Analog Dialogue HTML
Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
Technical Articles HTML
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Technical Articles HTML
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
Technical Articles HTML
Low-power direct digital synthesizer cores enable high level of integration Technical Articles HTML
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
Technical Articles HTML
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
Technical Articles HTML
DDS Device Provides Amplitude Modulation
by Mary McCarthy, Analog Devices, Inc.
(EDN, September 2, 1999)
Technical Articles HTML
Introducing Digital Up/Down Converters: VersaCOMM™ Reconfigurable Digital Converters  (pdf, 63 kB)
Revolutionize your radio architectures
Technical Articles PDF
Digital Up/Down Converters: VersaCOMM™ White Paper  (pdf, 97 kB) Technical Articles PDF
Basics of Designing a Digital Radio Receiver (Radio 101)  (pdf, 77 kB) Technical Articles PDF
The Year of the Waveform Generator
(Test & Measurement World, 12/1/2005)
Technical Articles HTML
Synchronized Synthesizers Aid Multichannel Systems
by David Brandon and John Kornblum, Analog Devices, Inc. (Microwaves & RF, 9/2005)
Technical Articles HTML
DDS Applications
by Eva Murphy and Colm Slattery, Analog Devices, Inc. (EETimes, 9/26/2005)
Technical Articles HTML
DDS IC Initiates Synchronized Signals
(Microwaves & RF Cover Story, July 2005)
Technical Articles HTML
DDS Simplifies Polar Modulation
By Ken Gentile, Analog Devices ... Basic modulation mathematics and DDS (direct digital synthesis) provide designers with an all-digital technique for generating polar-encoded carrier signals. (EDN, 8/5/2004)
Technical Articles HTML
Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement
by Colm Slattery, Analog Devices (EDN, 12/17/2004)
Technical Articles HTML
Integrated DDS Chip Takes Steps To 2.7 GHz
This highly integrated 2.7-GHz source includes all essential DDS circuitry along with a clock driver, divider, high-resolution DAC, and combination phase detector/charge pump. (ED Online, April 2004)
Technical Articles HTML
Two DDS ICs Implement Amplitude-shift Keying
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 12/25/2003)
Technical Articles HTML
DDS Circuit Generates Precise PWM Waveforms
by Colm Slattery, Analog Devices, Inc. (EDN, 10/2/2003)
Technical Articles HTML
DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 2/5/2004)
Technical Articles HTML
Simple Circuit Controls Stepper Motors
by Noel McNamara, Analog Devices, Inc. (EDN Design Idea, 1/8/04)
Technical Articles HTML
Digital Potentiometers Vary Amplitude In DDS Devices  (PDF)
(Electronic Design, Ideas for Design, 5/29/2000)
Technical Articles PDF
AD9858: Flexible Integrated Synthesizer For Wireless  (htm)
... The most important feature of the AD9858 is its ability to change frequency in less than 5 ns, meaning that there is virtually no application left where you will need to go the expense of switching between two separate synthesizers. (AnalogZone, RF/IF Zone Products for the Week of 9/23/2002)
Technical Articles HTM
DDS Device Produces Sawtooth Waveform
Ramp or sawtooth waveforms are useful for a broad range of applications, including automatic-test equipment, benchtest equipment, and actuator control. (EDN Design Idea, 7/10/2003)
Technical Articles HTML
400-MSample DDSs Run On Only +1.8 VDC
... This line of highly integrated DDS ICs features on-board RAM and crystal-oscillator circuitry to simplify the generation of agile and exotic waveforms. (Microwaves & RF Cover Story, 12/2002)
Technical Articles HTML
DDS Tackles BaseStations Head On
... This High-Performance, Low-Power Integrated Hybrid Synthesizer Flaunts A 10-b Digital-To-Analog Converter That Operates At Up To 1 GSample/s.
(Wireless Systems Design, September 2002)
Technical Articles HTML
Video Portables and Cameras Get HDMI Outputs
By Doug Bartow, Analog Devices, Inc.
Technical Articles HTML
Clock Requirements For Data Converters
(Electronic Design, 2/2005)
Technical Articles HTML
DDS Design
By David Brandon, Analog Devices, Inc.
Direct digital synthesizers are known for their highly accurate digital tuning, low noise figure, and phase-continuous frequency-hopping capabilities, which make them more attractive than alternative analog frequency-synthesis solutions.
(EDN, 5/13/2004)
Technical Articles HTML
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective  (pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
Technical Documentation PDF
Free Direct Digital Synthesis IC Evaluation Tool
(Control Engineering, 9/14/2006)
Product Reviews HTML
Where Analog Really Meets Digital
(EE Time, 8/29/2005)
Product Reviews HTML
On-Line Evaluation Tool Simplifies Implementing DDS Semiconductors
(eeProductCenter, 8/16/2006)
Product Reviews HTML
Circuit Simulation Tool Simplifies Clock Designs
(eeProductCenter, 8/23/2005)
Product Reviews HTML
Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04)
Product Reviews HTML
Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005)
Product Reviews HTML
Low Jitter Clock Generator for Data Converters
... Analog Devices' first dedicated clocking product supporting the stringent needs of high performance data converters. (AVNET Technology Review, November 2004, Vol. 10, Issue 11)
Product Reviews HTML
RF Source Booklet  (PDF, 4353 kB)
RF IC Product Overview - Version P (02/2014)
Overview PDF
Expanding Family of Integrated Clock ICs Overview HTML
Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks  (pdf, 64 kB) Overview PDF
Optical and High Speed Networking  (pdf, 2236 kB)
Analog Devices’ optical and high speed networking ICs solve a depth and breadth of challenges faced by today’s designers of datacom and telecom systems, optical modules, and subsystems. Analog Devices products address a wide range of networking applications from O/E/O conversion, clock recovery, and backplane transmission to monitoring and control of optical power, power management, and clock generation and distribution.
Overview PDF
Reset your thinking about clocks.  (pdf, 153 kB)
... In precision timing, analog is everywhere.
Overview PDF
Clock and Timing ICs  (pdf, 4970 kB) Overview PDF
My evaluation board is not working; the software is reporting a USB Communication Error. I verified that the evaluation board is connected to the PC and powered. What else can I check? FAQs/RAQs HTML
Why do I see reference spurs? FAQs/RAQs HTML
Why is my phase noise shape changing when I change the PLL settings? FAQs/RAQs HTML
Why doesn't the PLL make my reference input and the clock outputs line up? FAQs/RAQs HTML
How do I optimize my PLL loop for the best phase noise and/or jitter? FAQs/RAQs HTML
My loop is not locking. How do I debug this? FAQs/RAQs HTML
How long does it take for the PLL to lock? FAQs/RAQs HTML
Help! My PLL came unlocked over temperature. FAQs/RAQs HTML
How do I choose between active and passive filter in PLL loop? FAQs/RAQs HTML
Should I reference the passive filter to ground? or supply? FAQs/RAQs HTML
How do the PLLs in the AD951x parts compare to other ADI PLLs? FAQs/RAQs HTML
How does the clock clean-up function of the AD951x parts work? FAQs/RAQs HTML
Why do I want to run a fast PFD frequency? FAQs/RAQs HTML
Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? FAQs/RAQs HTML
Why can't I use a bandpass filter for my loop filter? FAQs/RAQs HTML
Should I tie my loop filter to ground or PLL supply? FAQs/RAQs HTML
The loop filter was working great until I changed the divide ratio in PLL. What happened? FAQs/RAQs HTML
How do I use a VCO with a supply greater than 5V? FAQs/RAQs HTML
What suppliers do you recommend for VCO/VCXOs? FAQs/RAQs HTML
Do VCXOs have better phase noise and jitter performance than VCOs? FAQs/RAQs HTML
How do I know which VCO will work best with the AD9510? FAQs/RAQs HTML
Is there an advantage to running a higher VCO frequency than the output frequency? FAQs/RAQs HTML
How do I determine if a VCO is good enough for my purpose? FAQs/RAQs HTML
Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? FAQs/RAQs HTML
Do different divide ratios cause variations in jitter? FAQs/RAQs HTML
I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? FAQs/RAQs HTML
Do divide ratios change the propagation delay? FAQs/RAQs HTML
I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? FAQs/RAQs HTML
On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? FAQs/RAQs HTML
Why doesn't the mini-divider support the divide ratio I want? FAQs/RAQs HTML
I want to use the variable delay adjust, but the jitter is too high. What can I do? FAQs/RAQs HTML
I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? FAQs/RAQs HTML
What is the difference between the coarse phase adjust and the fine delay adjust? FAQs/RAQs HTML
What is the fine delay adjust which is available on certain LVDS/CMOS outputs? FAQs/RAQs HTML
Does the fine delay adjust affect the jitter? FAQs/RAQs HTML
Why is the fine delay adjust not available on all the outputs? FAQs/RAQs HTML
Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? FAQs/RAQs HTML
Will the AD9510 work without a reference input signal? FAQs/RAQs HTML
What are the best clock sources for a distribution-only design? FAQs/RAQs HTML
I am not using the CLK1 input on the AD9510. Can I just leave it floating? FAQs/RAQs HTML
How good does my input signal need to be? FAQs/RAQs HTML
I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. FAQs/RAQs HTML
Can I shift the threshold on clocks for single-ended inputs? FAQs/RAQs HTML
The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? FAQs/RAQs HTML
Will differential or single-ended inputs/outputs improve my jitter? FAQs/RAQs HTML
Why should I use differential rather than single-ended? FAQs/RAQs HTML
How do I feed a single-ended signal into a differential input? FAQs/RAQs HTML
Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? FAQs/RAQs HTML
Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? FAQs/RAQs HTML
Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? FAQs/RAQs HTML
On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? FAQs/RAQs HTML
I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? FAQs/RAQs HTML
Can I use the 951X clocks to drive a mixer (RF LO)? FAQs/RAQs HTML
My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? FAQs/RAQs HTML
I have an input present at the clock input, but I'm not seeing an output? FAQs/RAQs HTML
What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? FAQs/RAQs HTML
What clock frequency comes out of the AD9510 outputs when you first apply power to the device? FAQs/RAQs HTML
Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) FAQs/RAQs HTML
I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? FAQs/RAQs HTML
What should I do with unused channels on the AD9510? FAQs/RAQs HTML
Can I tri-state the AD9510 outputs? FAQs/RAQs HTML
On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? FAQs/RAQs HTML
What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? FAQs/RAQs HTML
Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? FAQs/RAQs HTML
What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? FAQs/RAQs HTML
Does the AD9510 support 2.5V PECL? FAQs/RAQs HTML
How much bandwidth is required to process a PECL or LVDS output? FAQs/RAQs HTML
If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? FAQs/RAQs HTML
If I change the level of PECL output, does it affect the jitter? FAQs/RAQs HTML
What is the best way to terminate LVPECL outputs to get lowest jitter? FAQs/RAQs HTML
Is it okay to AC-couple PECL or LVDS outputs? FAQs/RAQs HTML
What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? FAQs/RAQs HTML
What is the proper termination (value and location) for outputs? FAQs/RAQs HTML
Are outputs short-circuit protected? FAQs/RAQs HTML
Are the CMOS drivers on the clock devices complementary? FAQs/RAQs HTML
Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? FAQs/RAQs HTML
I have pulled SYNCB low, but I still have output from a channel. Why? FAQs/RAQs HTML
Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? FAQs/RAQs HTML
The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? FAQs/RAQs HTML
May I use the AD9540 for spread spectrum clocking? FAQs/RAQs HTML
Can I get two clock outputs from the AD9540? FAQs/RAQs HTML
What's the advantage of a DDS-based clock generator? FAQs/RAQs HTML
Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? FAQs/RAQs HTML
I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? FAQs/RAQs HTML
On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? FAQs/RAQs HTML
How do you determine the bandwidth over which phase noise is integrated to obtain jitter? FAQs/RAQs HTML
Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? FAQs/RAQs HTML
How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? FAQs/RAQs HTML
When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? FAQs/RAQs HTML
How do you specify jitter? FAQs/RAQs HTML
How do I use the clock part for jitter clean-up? FAQs/RAQs HTML
If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? FAQs/RAQs HTML
Does jitter vary with different clock frequencies? How about phase noise? FAQs/RAQs HTML
I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? FAQs/RAQs HTML
Do you guarantee performance shown in ADIsimCLK? FAQs/RAQs HTML
Who do I contact for technical support on ADIsimCLK? FAQs/RAQs HTML
Should I use the minimum charge pump current settings in order to minimize power? FAQs/RAQs HTML
Can I run CMOS outputs at 5V? FAQs/RAQs HTML
Can I use different power supply voltages for the PECL output drivers? FAQs/RAQs HTML
Is .01 uF sufficient for power supply pin bypass? FAQs/RAQs HTML
My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? FAQs/RAQs HTML
Why don't you spec psrr and cmrr in the datasheet? FAQs/RAQs HTML
How do I get two AD951x (with PLL) to synchronize to the same reference input edge? FAQs/RAQs HTML
I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? FAQs/RAQs HTML
How do I synchronize multiple clock devices? FAQs/RAQs HTML
What happens if I run the part in an ambient environment which exceeds 85°C? FAQs/RAQs HTML
How can I determine the die temperature of your device? FAQs/RAQs HTML
My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? FAQs/RAQs HTML
What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? FAQs/RAQs HTML
Does Analog Devices offer a list of manufacturers of oscillators for DDS devices? FAQs/RAQs HTML
Where can I find some good background material on direct digital synthesis? FAQs/RAQs HTML
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

Design Tools,Models,Drivers & Software

Title Content Type File Type
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADIsim Design/Simulation Tools HTML

Evaluation Kits & Symbols & Footprints

Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.

SampleSample & Buy

Price, packaging, availability

AD9540 Model Options
Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

AD9540 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
Purchase/Sample
AD9540/PCBZ Status: Production Evaluation Board $250.00 Yes -
AD9540-VCO/PCBZ Status: Production Evaluation Board $250.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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