AD9670
RECOMMENDED FOR NEW DESIGNSOctal Ultrasound AFE With Digital Demodulator
Part Details
- 8 channels of LNA, VGA, antialiasing filter, ADC, and digital demodulator/decimator
- Low power
150 mW per channel, time gain compensation (TGC) mode, 40 MSPS
62.5 mW per channel, continuous wave (CW) mode; <30 mW in power-down mode - 10 mm × 10 mm, 144-ball CSP_BGA
- TGC channel, input referred noise voltage: 0.82 nV/√Hz, maximum gain
- Flexible power-down modes
- Fast recovery from low power standby mode: <2 μs
- Low noise preamplifier (LNA)
- Input noise voltage: 0.78 nV/√Hz, gain = 21.6 dB
- Programmable gain: 15.6 dB/17.9 dB/21.6 dB
- 0.1 dB input compression point: 1.00 V p-p/0.75 V p-p/ 0.45 V p-p
- Flexible active input impedance matching
- See data sheet for additional features
The AD9670 is designed for low cost, low power, small size, and ease of use for medical ultrasound applications. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an antialiasing filter, an ADC, and a digital demodulator and decimator for data processing and bandwidth reduction.
Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, antialiasing filter, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user-defined test patterns entered via the SPI.
Applications
- Medical imaging/ultrasound
- Nondestructive testing (NDT)
Software Resources
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| Parts | Product Life Cycle | Description |
|---|---|---|
| Analog to Digital Converters (ADCs) 1 | ||
| AD7982 | PRODUCTION | 18-Bit, 1 MSPS PulSAR ADC in MSOP/LFCSP |
| Clock ICs 6 | ||
| AD9510 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
| AD9511 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
| AD9512 | RECOMMENDED FOR NEW DESIGNS | 1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
| AD9513 | RECOMMENDED FOR NEW DESIGNS | 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9515 | RECOMMENDED FOR NEW DESIGNS | 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| Differential Amplifiers 2 | ||
| AD8138 | PRODUCTION | Low Distortion Differential ADC Driver |
| ADA4932-1 | RECOMMENDED FOR NEW DESIGNS | Low Power Differential ADC Driver |
| Fanout Buffers & Splitters 2 | ||
| ADCLK846 | RECOMMENDED FOR NEW DESIGNS | 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer |
| ADCLK946 | RECOMMENDED FOR NEW DESIGNS | Six LVPECL Outputs, SiGe Clock Fanout Buffer |
| Operational Amplifiers (Op Amps) 2 | ||
| ADA4896-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power, Rail-to-Rail Output Amplifiers |
| ADA4897-2 | RECOMMENDED FOR NEW DESIGNS | 1 nV/√Hz, Low Power Operational Amplifier |
Evaluation Kits
AD9670 Evaluation Board