Средства визуализации

The ADAS1134 is a 128-channel, current-to-digital, analog-to-digital converter (ADC). It contains 128 low power, low noise, low input current integrators, simultaneous sample-and-holds, and two high speed, high resolution ADCs with configurable sampling rate and resolutions up to 24 bits.

All converted channel results are output on a single, low voltage differential signaling (LVDS), self clocked serial interface, which reduces external hardware.

An SPI-compatible serial interface allows configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a single, 3-wire bus. The ADAS1134 uses IOVDD, a separate supply, to reduce digital noise effect on the conversions.

The ADAS1134 is available in a 10 mm × 10 mm, 242-ball CSP_BGA package.

Applications

• Medical, industrial, and security CT scanner data acquisition
• Photodiode sensors
• Dosimetry and radiation therapy systems
• Optical fiber power monitoring
• X-ray detection systems
• High channel count data acquisition systems (current or voltage inputs)

All converted channel results are output on a single, low voltage differential signaling (LVDS), self clocked serial interface, which reduces external hardware.

An SPI-compatible serial interface allows configuration of the ADC using the SDI_x input. The SDO_x output allows the user to daisy-chain several ADCs on a single, 3-wire bus. The ADAS1131 uses the separate supply, IOVDD, to reduce digital noise effect on the conversions.

The ADAS1131 is in a 15 mm × 15 mm, CSP_BGA package.

APPLICATIONS

• Medical, industrial, and security CT scanner data acquisition
• Photodiode sensors
• Dosimetry and radiation therapy systems
• Optical fiber power monitoring
• X-ray detection systems
• High channel-count data acquisition systems (current or
  voltage inputs)

All converted channel results are output on a single LVDS self-clocked serial interface that significantly reduces external hardware. An SPI-compatible serial interface allows configuration of the AFE using SDI input. The SDO output allows the user to daisy chain several AFEs on a single 3-wire bus.

An integrated AFE timing sequencer controls the sampling activity of the analog front end (AFE). The sequencer is programmed via the SPI port and is timed by a single clock, ACLK.

• Digital X-ray panel
• Photodiode sensors array
• CT Scanner
• High channel count data acquisition systems
  (current or voltage input)
• TFT panel readout

The AD9271 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amp-lifier (VGA) with low noise preamplifier (LNA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC).

Each channel features a variable gain range of 30 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 40 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.2 nV/√Hz, and the combined input-referred noise of the entire channel is 1.4 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is roughly 86 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 × 6 differential crosspoint switch. The switch is programmable through the SPI.

Applications

• Ease of design due to the drop-in LVDS isolator with fully compliant input/output and ultralow jitter.


• High bandwidth of 600 Mbps to support increased ADC resolution and speed.


• Galvanic isolation for protection from mains voltages, isolated measurement of power supplies, or noise immunity from digital or power supply circuits.

Figure 1. 18-Bit, 5 MSPS Signal Chain (All Connections and Decoupling Not Shown)

The circuit in Figure 1 is a two-channel, bank isolated, wide bandwidth data acquisition (DAQ) system, implemented with a simultaneous sampling architecture using an analog-to-digital converter (ADC) per channel. The system achieves high channel density along with isolation between the bank and the digital backplane, all while delivering exceptional performance. The design also makes efficient use of isolation channels by configuring the ADCs in daisy-chain mode and utilizing an isolator product with a trimmed delay clock feature. Power generation is also simplified using an isolator with an integrated pulse width modulation (PWM) controller and transformer driver to perform dc-to-dc conversion across the isolation barrier. The system also includes many common features of a typical DAQ signal chain, including input circuit protection, programmable gain channels, high accuracy, and high performance.

The simultaneous sampling realizes multiple channels without sample rate limitations inherent in multiplexed DAQ signal chains. The analog front end (AFE) design is also simpler than the multiplexed option, because the settling performance requirements of the system are less demanding. Sampling occurs simultaneously for each channel, while sequential sampling systems have delays between channels.

Digital bank isolated DAQ designs provide protection for digital back end circuitry and reduce ground loop and common-mode interference between banks. They feature multiple DAQ signal chains per ground plane, and can be implemented with fewer digital isolation devices than channel-to-channel isolated systems.

The circuit shown in Figure 1 is a cost effective, low power, multichannel data acquisition system that is compatible with standard industrial signal levels. The components are specifically selected to optimize settling time between samples, providing 18-bit performance at channel switching rates up to approximately 750 kHz.

The circuit can process eight gain-independent channels and is compatible with both single-ended and differential input signals.

The analog front end includes a multiplexer, programmable gain instrumentation amplifier (PGIA); precision analog-to-digital converter (ADC) driver for performing the single-ended to differential conversion; and an 18-bit, 1 MSPS PulSAR^® ADC for sampling the signal on the active channel. Gain configurations of 0.4, 0.8, 1.6, and 3.2 are available.

The maximum sample rate of the system is 1 MSPS. The channel switching logic is synchronous to the ADC conversions, and the maximum channel switching rate is 1 MHz. A single channel can be sampled at up to 1 MSPS with 18-bit resolution. Channel switching rates up to 750 kHz also provide 18-bit performance. The system also features low power consumption, consuming only 240 mW at the maximum ADC throughput rate of 1 MSPS.