How to Connect System Protection ICs for Higher Current Application

要約

Analog’s family of system protection ICs offers complete, highly integrated system protection solutions with up to 60VDC input operating voltage and output current ranging from 250mA to 6A in a single IC. While the individual ICs in this family address most single board applications, a multiboard system might need higher current beyond 6A. This application note illustrates higher current application (12A) by simply paralleling two of the 6A ICs together.

Introduction

This application note shows how to connect two 6A protection ICs together to achieve 12A current application. It discusses various design considerations and describes test results under different operating conditions. The MAX14691, a 60V, 6A power limiter is presented to illustrate common performance of Analog's 6A system protection IC family (MAX14691, MAX14692, MAX14693, MAX17525, MAX17526). The MAX14691 is configured for latchoff current-limit mode throughout the test.

Design Considerations

When paralleling two or more protection ICs together, the system designer should take into account how the ICs share output current under different operating conditions. Consider the IC’s performance during the following current-sharing conditions:

Startup with normal operation
Startup with high initial junction temperature
Output dynamic step load
Output dynamic step load to overload condition
Output short circuit
IC’s R_DS(ON) worst-case tolerance:
- In steady state
- During current limit

Design Example

In this example, we parallel two MAX14691 evaluation kits (EV kits) together. The current limit (ILIM) is set at 5.5A for each, for a total of 11A output current capability. Figure 1 shows the EV kit connection. The input voltage, output voltage, and each EV kit’s output currents are monitored while the system is subjected to various operating conditions. We test this protection system with a 24V input supply voltage and a large output capacitance of 3020µF (10µF on each EV kit and an additional 3,000µF on the common output). The EV kit is configured for latchoff current-limit mode (CLTS1 = CLTS2 = 0).

Figure 1. Paralleling two MAX14691 EV kits with VIN = 24V and COUT = 3020µF

Figure 1. Paralleling two MAX14691 EV kits with V_IN = 24V and C_OUT = 3020µF.

For complete EV kit specifications, see the MAX14691EVKIT data sheet.

Current Sharing Test Results

Startup with Normal Operation

Figure 2 shows the test result during normal startup with no output loading. The output currents I_OUT1 and I_OUT2 track each other very well, while the output voltage ramps up in a well-controlled manner. The output-voltage ramp rate is proportional to the total output current and inversely proportional to the output capacitance as follows:

Equation 1.

In other words, it will take 6.6ms to ramp linearly from 0V to 24V.

Figure 2. Current sharing during normal startup.

Startup with High Initial Junction Temperature

During startup, there is large power dissipation in the IC due to the voltage difference between V_IN and V_OUT, multiplied by the inrush current. Therefore, a high rise in temperature within the IC is expected. The MAX14691 features thermally controlled current-limit foldback to keep the die temperature within a safe operating limit.

To demonstrate this current-limit foldback feature, we repeatedly cycle the EV kits through the startup phase many times. After each startup time, the IC junction temperature rises to a higher value. Figure 3 illustrates the startup with high initial junction temperature where the thermally controlled, current-limit foldback function reduces the current limit to maintain the internal temperature at the +145°C threshold. As the output voltage builds up, the power dissipation drops, and the current limit returns to the full level until the output capacitor charges to V_IN.

Figure 3. Current sharing during startup when the IC’s initial junction temperature is high, showing the thermal foldback function in action.

The thermally controlled, current-limit foldback feature is very useful to guard the IC and the equipment it protects under unfavorable operating conditions such as unexpected high ambient temperature due to system fan(s) failure, fan inlet/outlet blockage, or room air conditioning failure.

Output Dynamic Step Load

Figure 4 shows the test result when the output current load steps from 0A to 10.5A. The output currents I_OUT1 and I_OUT2 also track each other very well in this condition, each sharing 5.25A, or half, of the load current.

Figure 4. Current sharing during a step load from 0 to 10.5A.

Output Dynamic Step Load to Overload Condition

Figure 5 illustrates the test result when an overload condition results from the output current stepping from 0A to 11.5A (resistive mode). Again, I_OUT1 and I_OUT2 track each other very well during this condition. Note that the current-limit loop has a limited bandwidth, resulting in an initial overshoot of I_OUT1 and I_OUT2 before nicely settling back to the current limit level of 5.5A each, totaling 11A. Because the load step of 11.5A demands a higher current than the set limit, the output voltage sags a bit. After the 24ms blanking time, the parts shut down, latch off, and assert the fault flag. Other choices for overcurrent response type besides latching off are auto-retry and continuous modes, which are user-selectable through the CLTS1 and CLTS2 pins.

Figure 5. Current sharing during a step load into an overload condition (11.6A).

To analyze how much output-voltage sag occurs during this resistive overload condition, use the following equations.

At 24V and 11.5A output, calculate the output resistive load as:

Equation 2.

At the current set limit of 11A, calculate the output-voltage sag as:

Equation 3.

Output Short Circuit

When there is an output short circuit, the output currents again share extremely well, as seen in the Figure 6 test result. It interesting to note that, during an output short circuit, power dissipation is very high in the current-limiting FET (power dissipation = [V_IN – V_OUT] × I_LIMIT). Again, the thermally controlled, current-limit foldback feature activates and reduces the current-limit level to keep the IC temperature within safe limits. After the 24ms blanking time, the ICs shut down just like during the overload condition.

Figure 6. Current sharing during an output short circuit.

R_DS(ON) Worst-Case Tolerance Finally, let’s examine how well the IC can current share, considering worst-case R_DS(ON) tolerance. As seen in the MAX14691 data sheet, the internal FET’s R_DS(ON) is 31m? (typ) and 42m? (max). Analog’s 6-sigma standard practice indicates that the standard deviation for this R_DS(ON) is 1.83m?, and 99.7% of the ICs will have their R_DS(ON) fall within 25.5m? and 36.5m?, or an 11m? worst-case tolerance spread.

To emulate this worst-case condition, we purposely add external resistance (R_EXT) to the power path of one of the evaluation kits. Table 1 shows the composition of the total resistance value in the power path. The external pFETs for reverse voltage/current protection are kept identical on both EV kits.

Table 1. Power Path Resistances
Power Path Resistances (Ω)	EV Kit 1	EV Kit 2
R_DS(ON) MAX14691 (mΩ)	30	31
R_DS(ON) external pFET (mΩ)	10	10
R_EXT (mΩ)	0	10
Total (mΩ)	R1 = 40	R2 = 51

R_DS(ON) Worst-Case Tolerance—Steady State Condition The current-sharing performance in a steady state condition is straightforward; it is similar to two resistors in parallel where the resistors are the total power path resistance of each EV kit. The current sharing is inversely proportional to the resistance, obeying Ohm’s Law:

Equation 4.

Working through the math, we find that:

Equation 5.

and

Equation 6.

Figure 7 shows the test result with I_OUT set to 10A:

Equation 7.

and

Equation 8.

Current-sharing performance considering RDS(ON) worst-case tolerance

Figure 7. Current-sharing performance considering R_DS(ON) worst-case tolerance—steady state condition.

R_DS(ON) Worst-Case Tolerance—During Current Limit

Now we apply a dynamic load to the system. Figure 8 shows the test result where the load current steps from 9A to 11.5A. The 11.5A (overload) period is less than the 24ms blanking time.

Figure 8. Current-sharing performance considering RDS(ON) worst-case tolerance step load from 9A to 11.5A (overload) is applied for less than the 24ms blanking time.

Figure 8. Current-sharing performance considering R_DS(ON) worst-case tolerance—step load from 9A to 11.5A (overload) is applied for less than the 24ms blanking time.

The current-sharing performance is divided into two sections, each governed by two distinct circuitries. The first section is during output loading less than the current limit (9A in this case). The internal FETs are fully on, and the power path resistance dictates the current-sharing performance, as shown in the steady-state section above. The second section is during output loading greater than the current limit (11.5A portion). The current-limit circuitry activates during this period, and its accuracy is specified in the data sheet as current limit accuracy (I_{LIM ACC}), which is ±10%. Since the overload condition is less than the 24ms blanking time, the IC does not shut down, and it resumes normal operation when the load current falls below the current limit threshold.

Figure 9 shows the result of a similar test, but this time the overload condition lasted longer than the 24ms blanking time. The outputs shut down after the 24ms blanking time.

Figure 9. Current-sharing performance considering IC's R<sub>DS(ON)</sub> worst-case tolerance. A step load of 11.5A (overload) is applied for greater than the 24ms blanking time.

Figure 9. Current-sharing performance considering IC’s R_DS(ON) worst-case tolerance. A step load of 11.5A (overload) is applied for greater than the 24ms blanking time.

Summary

We have examined the current-sharing capability of the MAX14691, configured for latchoff current-limit mode, under various operating conditions such as startups, steady state, dynamic loading, and fault loading. We have also considered the effects of temperature and IC’s worst-case R_DS(ON) mismatch.

In steady state, the current-sharing accuracy depends on the total power path resistance of the system, which consists of the R_DS(ON) of the IC’s internal FET and the R_DS(ON) of the external reverse-blocking pFET. Current sharing in this case is like two resistors in parallel, following Ohm’s Law.

In current-limit conditions, the parts share current, even with an R_DS(ON) imbalance. The current-sharing accuracy follows the current-limit accuracy (I_{LIM ACC}) specified in the data sheet, which is ±10% for the MAX14691. The MAX17526, a newer member of the family, has an even better current-limit accuracy of ±6%.

The MAX14691, which is exemplary of Analog’s 6A system protection IC family, can share current very well. To have system protection for a system requiring load current higher than 6A, just connect two of them in parallel. When paralleling, configure the IC’s for latchoff current-limit mode. Startup after a current fault in other modes (autoretry mode or continuous mode) might not be successful, since the start time is not synchronized due to possible timing mismatch between the devices.

For a complete list of Analog’s 6A system protection IC family, see Related Parts below.