LTspice: Modeling Safe Operating Area Behavior of N-channel MOSFETs


Often the most challenging aspect of Hot Swap™ circuit design is verifying that a MOSFET’s Safe Operating Area (SOA) is not exceeded. The SOAtherm tool distributed with LTspice IV® simplifies this task, allowing a circuit designer to immediately evaluate the SOA requirements of an application and the suitability of the chosen N-channel MOSFET.

SOAtherm may require a shift in your mindset concerning SOA. The output of the SOAtherm-NMOS model is the simulated silicon die temperature of the MOSFET. As circuit designers, we have become accustomed to thinking about SOA in terms of voltage, current, and time. It is easy to forget that SOA is determined by the peak die temperature of the MOSFET.

Verifying that a Hot Swap design does not exceed the capabilities of a MOSFET is a challenge at high power levels. Fortunately, thermal behavior and SOA may be modeled in circuit simulators such as LTspice. The SOAtherm-NMOS symbol included in LTspice contains a collection of MOSFET thermal models developed by Linear Technology to simplify this task. These thermal models can be used to verify that the MOSFET maximum die temperature is not exceeded, even in the Spirito region where allowable current falls off exponentially at high drain-to-source voltages. In theory, SOAtherm reports the temperature of the hottest point on the MOSFET die. SOAtherm models predict the temperature of the MOSFET without influencing the electrical behavior of the circuit simulation.

The SOAtherm models are based on the MOSFETs' datasheet information, and as such, are only as accurate as the manufacturers’ data. It is important to design with plenty of extra margin since the SOA curves provided by MOSFET manufacturers are frequently “typical” numbers without sufficient derating to account for part-to-part variation.

A word of warning before we begin the SOAtherm tutorial: don’t trust simulations that show parallel MOSFETs sharing SOA equally. This is only true in the ideal world of circuit simulators where the MOSFETs match perfectly. In the real world, there will be part-to-part variation between the MOSFETs, and one MOSFET may run away taking all of the current. When using parallel MOSFETs in SOAtherm, check that every single MOSFET out of a bank of MOSFETs is capable of handling the entire SOA event on its own. The exception is when an individual current limit is present for each parallel MOSFET, preventing any single MOSFET from running away.


The tutorial that follows takes about 15 minutes to complete and assumes a basic knowledge of LTspice operation. Typically, the SOAtherm-NMOS symbol is placed on top of the MOSFET in an LTspice schematic, and the case temperature and silicon die temperature are observed at the Tc and Tj pins respectively.

Start by opening the SOAtherm-NMOS Example schematic found in the right hand column on this page.

LTC4260 Example


Run this simulation. It steps through four different loading conditions at the output: 1Ω, 10Ω, 50Ω, and 100Ω. When you click on the output node, you should see the following waveform. The output powers up successfully into 10Ω, 50Ω, and 100Ω load. Into 1Ω, it detects the excessive loading at the output and does not ramp up fully. It retries every 150ms into the 1Ω load.

LTC4260 Example Plots

LTC4260 Example Plot

Press F2 and select the SOAtherm-NMOS symbol.

SOAtherm-NMOS Select


SOAtherm-NMOS Symbol

Place the SOAtherm-NMOS symbol on top of the NMOS symbol already in the schematic. Use CTRL-R to rotate the symbol. The SOAtherm-NMOS symbol is used as an overlay and the NMOS symbol should not be deleted. 

Add SOAtherm-NMOS Symbol


SOAtherm-NMOS Symbol

After placing the symbol on top of the MOSFET, the extra wires should be deleted automatically. If the wires are not deleted automatically, delete them manually by pressing F5 and clicking on each one. Alternatively, open the SOAtherm-NMOS Tutorial 1 where these steps have already been completed.

Overlay of SOAtherm Symbol


SOAtherm-NMOS Symbol on NMOS Symbol

Now that the SOAtherm-NMOS symbol has been placed in the schematic, the appropriate MOSFET thermal/SOA model must be selected. To change the model, right-click on the symbol near the current meter of the SOAtherm-NMOS symbol to avoid selecting the overlapping NMOS symbol. Then, right-click on the SpiceModel cell. It will show a drop-down menu of existing SOAtherm-NMOS models. You must right-click or double-click to see the drop-down menu. For this simulation, select the PSMN4R8100BSE which matches the NMOS symbol already placed in the schematic. If you are using the Mac version of LTspice you can left-click to make the field editable and paste the MOSFET name directly into the SpiceModel field.

SOAtherm-NMOS Attribute Editor

SOAtherm-NMOS Attribute Editor

Now, add two named nets, Tj-FET and Tc-FET, and connect these to the Tj and Tc pins of the SOAtherm-NMOS symbol. You can use F3 to add wire and F4 to insert a label net. The net name is unimportant, it could be anything.

SOAtherm-NMOS Symbol with Nets

SOAtherm-NMOS Symbol with Nets

Run the simulation again and plot the voltage of the Tj-FET node. The voltage at the Tj-FET node represents the junction temperature in °C. The Tj-FET temperature reaches a maximum of 132°C in this simulation, and it started from 85°C. Why does it start at 85°C? The ambient temperature has an 85°C default in this symbol. Next, we will change the ambient temperature to 70°C.

LTC4260 SOAtherm Tj Plot

LTC4260 SOAtherm Tj Plot

Right-click on the symbol and change the Tambient=85 value to Tambient=70. Alternately, open SOAtherm-NMOS Tutorial 2 where this has already been completed.

SOAtherm-NMOS Attribute

SOAtherm-NMOS Attributes

Run the simulation again, and you will see that the peak junction temperature is now 123°C.

LTC4260 SOAtherm Tj Plot with Ta = 70°C

LTC4260 SOAtherm Tj Plot with Ta = 70°C

The PSMN4R8100BSE MOSFET has an allowed maximum junction temperature of 175°C according to the datasheet. Most MOSFETs have a maximum junction temperature of 150°C or 175°C.

What does this simulation show us? First, the maximum junction temperature is less than 175°C, so this meets the SOA limits in the datasheet, and the worst-case loading condition resulted in a 50°C junction temperature rise. As mentioned previously, MOSFET manufacturer datasheet limits for SOA are often typical values requiring extra design margin to avoid pushing a MOSFET to the edge of its rated limits.

Let’s try one more test. Change the GATE capacitor from 10nF to 100nF, and run the simulation again.

Editing Gate Capacitance

Editing Gate Capacitance

Observe the Tj-FET waveform.

LTC4260 SOAtherm Tj Plot with Cg = 100nF

LTC4260 SOAtherm Tj Plot with Cg = 100nF

You will see that the maximum temperature of the MOSFET is now over 300°C when the load is 1 ohm. Obviously, this is not a good idea. The slow ramp on the GATE results in MOSFET heating, but it is not yet in current limit where the LTC4260 timer starts to run.

Change the capacitor back to 10nF, and run the simulation again. Look at the Tc-FET node this time. This is the case temperature of the MOSFET. With a 1ohm load and autoretry enabled, the case temperature walks up with each retry. If this is a possible scenario in your application, either disable autoretry, or ensure that the PCB layout/fan provides adequate cooling. The next “advanced” section will show how to adjust the RθJA parameter to account for improved PCB and airflow cooling.

LTC4260 SOAtherm Tc Plot

LTC4260 SOAtherm Tc Plot

It is recommended that you also open the LTspice SOAtherm Model Index Speadsheet which contains a list of supported MOSFETs along with plots of the simulated SOA and the datasheet SOA. In addition, the spreadsheet allows convenient sorting of the MOSFETs by RDS(ON), maximum VDS, maximum ID, or SOA rating.) Lastly, don’t forget that while simulations are a useful tool, they are not a substitute for solder and an oscilloscope.


Every SOAtherm-NMOS library model contains a default RθJA value from the MOSFET manufacturer’s datasheet. When necessary, RθJA can be changed by adding an RthetaJA attribute (see Component Attribute Editor example below). For examples of board area and cooling effects on RθJA, please refer to the LT3080 datasheet section Thermal Considerations.

The SOAtherm-NMOS library models do not assume any heatsinking from the PCB or an external heatsink. They only include the heatsinking due to the copper tab/paddle inside the MOSFET. The “Cheatsink” parameter may be used to add extra heatsinking to the model. Every 1mm3 of copper results in 0.00345F for Cheatsink. For example, a 500mm3 copper heatsink results in Cheatsink=1.7. Alternatively, you can connect R’s and C’s at the Tc pin of your schematic, and they will appear in parallel with the internal components.


Add RthetaJA=10 to the SOAtherm symbol’s attribute in the previous schematic and run the simulation again for 60 seconds with .tran 0 60 0. If you have trouble completing these steps, open the schematic SOAtherm-NMOS Tutorial 3

SOAtherm-NMOS Attributes Modification

Advanced SOAtherm-NMOS Attributes

This time the Tc-FET, case temperature, rises to 25°C above ambient. This is because the MOSFET is dissipating an average of 2.5W during retry and the RθJA is 10C/W.

LTC4260 SOAtherm Tc Plot with RthetaJA=10

LTC4260 SOAtherm Tc Plot with RthetaJA=10

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Dan Eddleman

Dan Eddleman is an analog engineer with over 15 years of experience at Linear Technology as an IC designer, the Singapore IC Design Center Manager, and an applications engineer.

He began his career at Linear Technology by designing the LTC2923 and LTC2925 Power Supply Tracking Controllers, the LTC4355 High Voltage Dual Ideal Diode-OR, and the LTC1546 Multiprotocol Transceiver. He was also a member of the team that designed the world’s first Power over Ethernet (PoE) Controller, the LTC4255. He holds two patents related to these products.

He subsequently moved to Singapore to manage Linear Technology’s Singapore IC Design Center, overseeing a team of engineers that designed products including Hot Swap controllers, overvoltage protection controllers, DC/DC switched-mode power supply controllers, power monitors, and supercapacitor chargers.

Upon returning to the Milpitas headquarters as an applications engineer, Dan created the Linduino, an Arduino-compatible hardware platform for demonstrating Linear Technology’s I2C- and SPI-based products. The Linduino provides a convenient means to distribute C firmware to customers, while also providing a simple rapid prototyping platform for Linear Technology’s customers.

Additionally, in his role as an applications engineer, he conceived of the LTC2644/LTC2645 PWM to VOUT DACs, and developed the XOR-based address translator circuit used in the LTC4316/LTC4317/LTC4318 I2C/SMBUS Address Translators. He has applied for patents related to both of these products. Dan has also developed multiple reference designs that satisfy the onerous MIL-STD-1275 28V military vehicle specification.

Dan continues to study Safe Operating Area of MOSFETs, and has created software tools and conducts training sessions within Linear Technology related to SOA. His SOAtherm model distributed with LTspice allows customers to simulate MOSFET SOA within their Hot Swap circuit simulations using thermal models that incorporate Spirito runaway.

He received an M.S. in Electrical Engineering from Stanford University and B.S. degrees in Electrical Engineering and Computer Engineering from the University of California, Davis.


Gabino Alonso

Gabino Alonso is currently the director of strategic marketing for the Power by Linear™ Group. Prior to joining ADI, Gabino held various positions in marketing, engineering, operations, and education at Linear Technology, Texas Instruments, and California Polytechnic State University. He holds a Master of Science degree in electrical and computer engineering from University of California, Santa Barbara.