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Evaluation Hardware

Part Numbers with "Z" indicate RoHS Compliance. Boards checked are needed to evaluate this circuit.

  • EVAL-CN0158-EB1Z ($82.39) Universal Serial Bus USB Hub Isolator Circuit
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Features & Benefits

  • Isolates and multiplexes two devices into a single USB port
  • Standard USB interface

Circuit Function & Benefits

The universal serial bus (USB) is rapidly becoming the standard interface for most PC peripherals. It is displacing RS-232 and the parallel printer port because of superior speed, flexibility, and support of device hot swap. There has been a strong desire on the part of industrial and medical equipment manufacturers to use the bus as well, but adoption has been slow because there has not been a good way to provide the isolation required for connections to machines that control dangerous voltages or low leakage defibrillation proof connections in medical applications.

The ADuM4160 is designed primarily as an isolation element for a peripheral USB device. However, there are occasions when it is useful to isolate a host device. Several issues must be addressed to use the ADuM4160 for this application. Whereas the buffers on the upstream and downstream sides of the ADuM4160 are the same and capable of driving a USB cable, the downstream buffers must be capable of adjusting speed to a full or low speed peripheral that is connected to it.

Unlike the case of building a dedicated peripheral interface where the speed is known and not changed, host applications must adapt. The ADuM4160 is intended to be hardwired to a single speed via pins; therefore, it works when the peripheral plugged into its downstream side is the correct speed, but it fails when the wrong speed peripheral is attached. The best way to address this is to combine the ADuM4160 with a hub controller.

The upstream side of a hub controller can be thought of as a standard fixed speed peripheral port that can be easily isolated with the ADuM4160, whereas the speed of the downstream ports is handled by the hub controller. The hub controller converts peripherals of different speeds to match the upstream port speed. The circuit shown in Figure 1 shows how a two-port hub chip can be used to isolate two downstream host ports in a design that can be made fully compliant with the USB specification.

Figure 1. USB Cable Isolator Circuit


The ADuM4160 provides an inexpensive and easy to implement isolation buffer for medical and industrial peripherals. The challenge that must be met is to use this to create a fully com-pliant host port by pairing the ADuM4160 with a hub chip. As with isolating any peripheral device, the services that the ADuM4160 and hub provide are as follows:

  1. Directly isolates, in the upstream, the USB D+ and D− lines of a hub chip, allowing the hub to manage the downstream host port activity.
  2. Implements an automatic scheme for data flow of control that does not require external control lines.
  3. Provides medical grade isolation.
  4. Allows creation of one or more host ports that meet the USB-IF certification standards.
  5. Supports full speed signaling rates.
  6. Supports flexible power configurations.

The goal of the application circuit is to isolate a hub as if it were a full speed peripheral device. The hub or host function requires that 2.5 W of power be available to each downstream port. Power to run the downstream side of the isolator and power the hub and ports is provided as part of the solution. The application circuit is typical of many medical and industrial applications.

Circuit Description

Power for the upstream USB connector is derived from the 5 V VBUS voltage available on the USB cable. The hub chip must provide all of the signals and pull-up or pull-down resistors that would be required if the ADuM4160 were not present. The hub chip chosen is an SMSC USB2512 two-port USB hub controller. This part was chosen because of its low cost and small footprint. In addition, a 4-channel version is available in the same footprint. The design is full featured, supporting channel by channel current limiting through a MIC2026 power distribution switch and sufficient offline regulated power to provide 2.5 W to each downstream channel. Power on the downstream side is provided by a wall wart and an ADP3339 LDO regulator (5 V option). This component provides very low dropout voltage, reducing the regulation requirements on the "wall wart".

Its small size and 1.5 A current capability are ideal for this general-purpose circuit where the peripherals downstream may require full cable power to operate.

The ADuM4160 has several options for power speed and protection that must be determined. Peripheral devices run at one of three speeds, low (1.5 Mbps), full (12 Mbps), and high (480 Mbps). The ADuM4160 does not support high speed operation and blocks handshaking signals that are used to negotiate that speed. The hub chip chosen supports high speed operation, but this mode is not allowed by the normal operation of the ADuM4160. The ADuM4160 must be set to operate at full speed via the state of the SPU and SPD pins. In the current schematic, the SPU and SPD pins are tied to the regulated 3.3 V power supplies, VDD1 and VDD2, setting the part for full speed operation.

Power can be provided as 5 V through the VBUSx pins. The 3.3 V signaling voltage is created by an internal 3.3 V regulator at the VDDx pin. Another option is to supply 3.3 V directly to both VBUSx and VDDx. The part senses this configuration and disables the internal regulator using the 3.3 V supply directly. For illustrative purposes, the downstream side of the ADuM4160 is configured to accept a 3.3 V external supply, bypassing the internal regulator. The VBUS2 and VDD2 pins are shorted together and supplied with an external 3.3 V generated by an ADP3330 LDO regulator.

The ADuM4160 has an option to delay application of the upstream pull-up under control of the peripheral. This function is controlled by the PIN input. In this application, the PIN input is shorted high so that the upstream pull-up is applied as soon as power is applied to the hub chip. In some applications, it can be connected to a GPIO pin of a controller, a fixed delay circuit can be applied, or it can be connected as in this circuit. It is the designer’s choice how to use this functionality.

EOS/ESD protection devices are represented in this circuit. These were chosen from manufacturers that have a wide variety of components available; the particular components were chosen to allow them to be replaced by 0 Ω shorts, removing them from the circuit. The choice of protection should be reviewed by the designer and can range anywhere from not needing external protection to needing a full complement of transient suppressors and filter elements. The circuit elements included in this application are typical of what can be used.

When the circuit is functioning, packets are detected and data is shuttled from one side of the isolation barrier to the other. Data shown in Figure 2 and Figure 3 demonstrates a typical full speed transaction both as time domain data and as an eye diagram. Features to note in the real-time data are the passive idle state at the start of the packet, which transitions to a driven J and then the end of packet at the end of the transaction showing as a single-ended zero state followed by an idle J. It is the automatic flow of control and the handling of these special logic states that make the ADuM4160 chip possible and unique in the marketplace.

Figure 2. Full Speed Test Packet Traffic Driven by the Upstream ADuM4160 Port


This hub design is fully isolated from the upstream data con-nection for transients up to 5 kV. The downstream ports are powered through an offline power source to support full power applications. Low, full, and high speed peripherals can be connected to the downstream ports in any combination; the hub controller properly negotiates speed based on the USB standard. The design also includes current switching and limiting as well as positions for other output protection devices that can be installed as the designer chooses.

The following are applicable test references:

  • Upstream full speed signal quality test reference—USB 2.0 Specification, Section 7.1.11., Section
  • Upstream full speed rise time test reference—USB 2.0 Specification, Section 7.1.11., Section
  • Upstream full speed fall time test reference—USB 2.0 Specification, Section 7.1.11., Section

Figure 3 is a full speed eye diagram showing that the ADuM4160 provides an adequate open eye, staying well out of the keep out region. There is an exception for a single transition that violates the keep out zone. This type of artifact is acceptable to qualification in this test. Similar data is taken for low speed evaluation as well. A photograph of the board is shown in Figure 4. A complete design support package for this circuit note can be found at http://www.analog.com/CN0158-DesignSupport.

Figure 3. Full Speed Eye Diagram Showing the Exclusion Zone


Figure 4. ADuM4160 Isolated USB Hub Evaluation Board

Common Variations

Other linear regulators can be substituted, depending on system requirements. Refer to the ADIsimPower™ design tool for details.

Circuit Evaluation & Test

The ADuM4160 isolated USB hub evaluation board is specifically developed to evaluate and test the circuit described in this Circuit Note. A detailed schematic and picture of the circuit board are shown in Figure 1 and Figure 4.

Equipment Needed

The following equipment is needed: a USB port hub connection, with an upstream-downstream data path, the ADuM4160 isolated USB hub, the ADuM4160 evaluation board, three USB cables, and a high speed digital oscilloscope.

Getting Started

In addition to the circuit, circuit schematic, and block diagram of the test setup described in this Circuit Note, details regarding the ADuM4160 isolated USB hub evaluation board, Gerber’s, bill of materials, layout, and assembly information are contained in the CN-0158 design support package. Information regarding the components used in the isolator circuit is available in the ADuM4160, ADP3330, and ADP3339 data sheets and the ADuM4160 evaluation board user guide, UG-043.

Functional Block Diagram

See Figure 1 for the schematic of the described test setup.