Active Biasing Solution for pHEMT Power Amplifiers

Abstract

Pseudomorphic high electron mobility transistors (pHEMT) are depletion devices that have drain-source channels with resistances close to 0 Ω. This property allows the devices to operate at high gain at high switching frequencies. However, the high conductivity of the drain channel might result in a burnout on the devices if a proper gate and drain bias sequencing is not applied. In this article, we will explore the operation of depletion mode pHEMT radio frequency (RF) amplifiers and how they can be practically biased. Depletion mode field-effect transistors (FETs) require a negative gate voltage and turn on/off must be carefully sequenced. Fixed gate voltage and fixed drain current circuits will be presented and compared. We will also take a close look at how the noise and spurs of these biasing circuits affect RF performance.

Introduction

Figure 1 shows a simplified block diagram of a depletion mode pHEMPT RF amplifier. The RF signal path through the device is from gate to drain with AC-coupling capacitors to decouple the RF signal from the DC bias voltages on the drain and gate. The main supply voltage is applied to the drain of the FET transistor through an inductor.

Figure 1. A simplified architecture of a depletion mode RF amplifier.

One important property of depletion mode devices is that the drain-to-source resistance is close to 0 Ω when the gate voltage is equal to 0 V. As a result, to operate the device, a negative voltage must be applied to the gate. In Figure 1, this voltage is applied through an on-chip inductor.

One drawback of this biasing method is that the two supplies cannot be turned on at the same time. Applying a drain bias voltage before the gate bias voltage causes a sudden increase in drain current that will quickly cause burnout. Because of this, a negative gate bias voltage must first be applied to pinch off the channel. When turning the amplifier on and off, the procedures in Table 1 should be used.

Table 1. Amplifier Procedures
Power-On Sequence Power-Off Sequence
1. Apply the negative voltage to the gate placing the gate in pinch-off mode. 1. Remove the RF signal.
2. Apply the positive voltage to the drain. 2. Decrease the gate voltage (more negative) to pinch off the gate.
3. Increase the gate voltage to achieve the quiescent current. 3. Reduce the drain voltage to 0 V.
4. Apply the RF signal. 4. Increase the gate voltage to 0 V.

In practice, the pinch-off step can be skipped. For example, if the final gate voltage for normal operation is known, that voltage can be immediately applied without going through the pinch-off step.

Fixed Gate Voltage Biasing

Figure 2 shows a power management circuit for a depletion mode RF amplifier that establishes and maintains a fixed gate voltage. This uses a switching regulator, low dropout (LDO) regulator, and load switch to develop the drain voltage. The gate voltage is developed by the ADP5600, which contains a voltage inverter and an LDO regulator. The drain current is set by the feedback resistors of the negative voltage LDO regulator. To ensure safe power sequencing, the enable (EN) pin of the switching regulator is tied to the power good (PGOOD) signal of the negative voltage generator. This ensures that the negative gate voltage is always present before the drain voltage.

Figure 2. Fixed gate voltage biasing.

The main disadvantage of this circuit is that it does not take into account the part-to-part variation in the VGATE to IDRAIN relationship of the RF amplifier. The part-to-part variation in drain current (assuming a fixed gate voltage) can be significant resulting in each circuit having a different drain current. Drain current variations typically impact compression (OP1dB) and third-order intermodulation distortion (OIP3) (gain will also be affected but to a lesser extent). One benefit of this approach is that the drain current will increase and decrease based on the RF input and RF output power present. So if the RF input power is low, power consumption will be low and vice versa.

Active Bias Control

Active bias control is an alternative approach. Instead of fixing the gate voltage, this technique involves fixing the drain current. In Figure 3, an active bias controller regulates the drain current by measuring that current and varying the gate voltage to keep the current fixed even at different input RF conditions. The circuit consists of an LT8608 step-down regulator and the HMC920 active bias controller which can support drain voltages from 3 V to 15 V and total drain currents of up to 500 mA.Active bias control is an alternative approach. Instead of fixing the gate voltage, this technique involves fixing the drain current. In Figure 3, an active bias controller regulates the drain current by measuring that current and varying the gate voltage to keep the current fixed even at different input RF conditions. The circuit consists of an LT8608 step-down regulator and the HMC920 active bias controller which can support drain voltages from 3 V to 15 V and total drain currents of up to 500 mA.

Figure 3. Fixed drain current biasing (active bias control).

The high voltage, high current linear regulator (LDOCC pin) inside the HMC920 can generate positive voltages from 3 V to 15 V and current up to 500 mA. Its output is connected to the VDRAIN port via an internal MOSFET switch, which is used for power sequencing. To set the desired drain voltage for the power amplifier, the feedback resistors of the LDO regulator, R5 and R8, must be adjusted using Equation 1:

Equation 1

Where VDRAIN is the desired drain voltage value and IDRAIN is the desired drain current. The 0.5 constant is the RDS(ON) value of the internal MOSFET switch.

The internal charge pump generates the negative voltage for VGATE. By reading the voltage at RSENSE, the controller senses the drain current and varies the voltage at VGATE. To set the drain current, RSENSE (R4 and R19) must be varied using Equation 2:

Equation 2

When HMC920 is turned on by applying the supply voltage (VDD), a signal will be sent to the EN pin to start the control loop. VDRAIN is initially shorted to the ground to force it to zero. Meanwhile, the voltage at the VGATE is initially pulled to the minimum voltage of VNEG. After this, VDRAIN will increase to the drain voltage value that was set. A voltage drop will be generated on RSENSE, which will result in the controller to vary the gate voltage. During turn-off, a logic low signal will be sent to the EN pin. VGATE will decrease to VNEG to cut off the amplifier and the voltage at VDRAIN will decrease to zero. The voltage at VGATE will eventually reach zero. This cycle follows the proper power sequencing for the safe operation of depletion mode amplifiers. It also has safety features such as over and under current alarm, short circuit protection, and power foldback. Other safety mechanisms of the bias controller are explained in detail in the HMC920 data sheet.

This bias controller was implemented as a power management solution for the ADL8106 wideband low noise amplifier. The ADL8106 operates from 20 GHz to 54 GHz with a nominal drain voltage of 3 V and a quiescent drain current of 120 mA. Figures 4 and 5 show the associated turn on and turn off waveforms.

Figure 4. Power sequencing waveforms at turn on. Once VDD is applied, high EN signifies the start of the control loop. VGATE is turned ON first, followed by the VDRAIN.
Figure 5. Power sequencing waveforms at turn off. When VDD is removed, EN will be low. VGATE will decrease to the minimum VNEG again and VDRAIN will decrease to zero. Then VGATE will eventually reach zero.

Noise and Spur Suppression

The level of spurs and noise at the RF output of the RF amplifier will depend on the output noise and spurs of the HMC920 and on the power supply modulation ratio (PSMR) of the amplifier. Figure 6 shows the plots of the PSRR at the switching regulator (LT8608) inputs and the VDRAIN and VATE output ports. Figures 7 and 8 show the output spectrum of the VGATE and VDRAIN voltages. Based on the PSMR of ADL8106, traces have also been included in these plots which show the maximum allowable output noise and spurs. The output noise and spurs from the power management circuit must be below these levels to ensure that the amplifier’s performance is not degraded by the power management circuit. For a more in-depth explanation of the theories, measurement, and calculation of this parameter, see the Optimizing Power Systems for the Signal Chain article series.

Figure 6. The power supply rejection ratio of the LT8608 + HMC920 (VDD = 5 V, VDRAIN = 3 V, IDQ = 120 mA, VGATE = –0.64 V).
Figure 7. The output spectra of the HMC920’s VGATE and VDRAIN outputs and maximum allowable noise limits for the ADL8106.
Figure 8. The output spectra of the HMC920’s VGATE and VDRAIN outputs and maximum allowable noise limits for the ADL8106.

Operating HMC920 with an External Negative Supply

In the previous example, the HMC920’s internal negative voltage generator is used to generate the negative gate voltage. An external negative supply can also be used as shown in Figure 9. In this case, the ADP5600 (inverter and negative LDO regulator) is used as the negative supply from which the gate voltage is derived. This result is a slightly lower noise figure and higher gain compared to when the internal negative voltage generator is used.

Figure 9. The ADL8106 and the HMC920 at the external VNEG mode block diagram.
Figure 10. The noise figure of the ADL8106 using the HMC920 at the internal negative voltage generator mode and on the external negative voltage generator mode.
Figure 11. The gain of the ADL8106 using the HMC920 at the internal negative voltage generator mode and on the external negative voltage generator mode.

The actual noise performance in this mode still depends on the output noise produced by the external negative voltage generator used. As seen from figures 7 and 8, using HMC920 at external VNEG mode also produces noise spurs that are still below the maximum allowable voltage ripple limit. To utilize this mode, the feedback control of the negative voltage generator must be disabled by sorting the VNEGFB pin to the ground. For enhancement type amplifiers (positive gate voltage), both the VNEGFB and VGATEFB pins must be connected to the ground.

Conclusion

Depletion mode GaAs amplifiers are widely used in RF applications because of their wide bandwidth and high dynamic range. But they need a negative bias voltage and must be carefully sequenced. A fixed negative gate voltage can be used to bias the amplifier. This has the benefit that current consumption is dynamic and scales with the RF output level. The circuit presented here uses a fixed drain current and generates low noise drain and gate voltages that are safely sequenced and which do not degrade the specified performance of the RF amplifier. It will result in tighter device-to-device performance because every device is operating from the same drain current. However, one downside of this approach is that the drain current is fixed and does not scale with the RF power level. Care and consideration should be taken in deciding on the fixed drain current level, which must be high enough to support the maximum desired output power level but not so high that it results in current wastage. While an external negative supply can be used to override the internal negative voltage generator of the HMC920, the resulting improvement in noise is marginal.

Author

Gweneivere Lasay

Gweneivere Lasay

Gweneivere Lasay graduated from Mapua University in 2017 with a bachelor’s degree in electronics engineering. She has more than 4 years of professional experience in the field of power semiconductors and SMPS design. She joined Analog Devices in March 2022 as a product applications engineer with the RF and High Speed Power Attach Group.