OP17

The PMI JFET-input series of devices offer clear advantages over industry-generic devices and are superior in both cost and performance to many dielectrically-isolated and hybrid op amps. All devices offer offset voltages as low as 0.5mV with TCV_OS guaranteed to 5µV/°C. A unique input bias cancellation circuit reduces the I_B by a factor of 10 over convential designs. In addition, PMI specifies 1_B and I_OS with the devices warmed up and operating at 25°C ambient.

These devices were designed to provide real precision performance along with high speed. Although they can be nulled, the design objective was to provide low offset-voltage without nulling. Systems generally become more cost effective as the number of trim circuits is decreased. PMI achieves this performance by use of an improved Bipolar compatible JFET process coupled with ono-chip, zener-zap offset trimming.