Overview

Features and Benefits

  • Simplifies RF Design and Enables New Communication Architectures
    • Eliminates I/Q Imbalance and LO Feedthrough
    • Enables Multi-Band RF Modulation
  • Direct RF Synthesis of 600MHz Bandwidth Up to 2.8GHz
    • 5.898Gsps DAC Output Update Rate
    • High-Performance 14-Bit RF DAC Core
    • Digital Quadrature Modulator and NCO with 1Hz/10Hz/100Hz/1kHz/10kHz Resolution
    • 5x/6x/6.67x/8x/10x/12x/13.33x/16x/20x/24x Interpolation
    • Integrated Clock Multiplying PLL+VCO
  • Highly Flexible and Configurable
    • 1, 2, or 4-Lane JESD204B Input Data Interface
      • Subclass-0 and Subclass-1 Compliant
      • Up to 10Gbps Per Lane
    • Reference Clock for System Synchronization
    • Multiple DAC Synchronization (Subclass-1)
    • SPI Interface for Device Configuration

Product Details

The MAX5869 high-performance interpolating and modulating 16-bit 5.9Gsps RF DAC can directly synthesize up to 600MHz of instantaneous bandwidth from DC to frequencies greater than 2.8GHz. The device is optimized for digital video broadcast and cable applications and meets spectral mask requirements for a broad set of communication standards including DVB-T, DVB-T2, DVB-C2, DVB-S2, DVB-S2X, ISDB-T, EPoC, and DOCSIS 3.0/3.1.

The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL+VCO and a 14-bit RF DAC core. The user-configurable 5x, 6x, 6.67x, 8x, 10x, 12x, 13.33x, 16x, 20x or 24x, linear phase interpolation filters simplify reconstruction filtering, while enhancing passband dynamic performance, and reduce the input data bandwidth required from an FPGA/ASIC. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis.

The MAX5869 accepts 16-bit input data via a four-lane JESD204B SerDes data input interface that is Subclass-0 and Subclass-1 compliant. The interface can be configured for 1, 2, or 4 lanes and supports data rates up to 10Gbps per lane allowing flexibility to optimize the I/O count and speed.

The MAX5869 clock input has a flexible clock interface and accepts a differential sine-wave, or square-wave input clock signal. A bypassable clock multiplying PLL and VCO can be used to generate a high-frequency sampling clock. The device outputs a divided reference clock to ensure synchronization of the system clock and DAC clock. In addition, multiple devices can be synchronized using JESD204B Subclass-1.

The MAX5869 uses a differential current-steering architecture and can produce a 0dBm full-scale output signal level with a 50Ω load. Operating from 1.8V and 1.0V power supplies, the device consumes 2.5W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).

Applications

  • Digital Video Broadcast:
    DVB-T/DVB-T2/ISDB-T Modulators,
    DVB-C2/DVB-S2/DVB-S2X Modulators
  • Downstream DOCSIS CMTS Modulators
  • Ethernet PON over Coax (EPoC)

Product Lifecycle icon-recommended Production

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.