MAX5857
16-Bit, 5.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
Direct RF Synthesis of 1200MHz Instantaneous Bandwidth from DC to Greater than 2.6GHz
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Overview
Features and Benefits
- Simplifies RF Design and Enables New Communication Architectures
- Eliminates I/Q Imbalance and LO Feedthrough
- Enables Multi-Band RF Modulation
- Direct RF Synthesis of 1.2GHz Bandwidth
- 5.898Gsps DAC Output Update Rate
- High-Performance 14-Bit RF DAC Core
- Digital Baseband I/Q with 4x Interpolation
- Bypass Path Without Interpolation for Real RF
- Digital Quadrature Modulator+NCO for Full Agility
- Sub-1Hz NCO Resolution
- Integrated Clock Multiplying PLL+VCO
- Highly Flexible and Configurable
- 3, 4, 5, or 6-Lane JESD204B Input Data Interface
- Subclass-0 Compliant
- Up to 9.8304Gbps Per Lane
- Divided Reference Clock Output
- SPI Interface for Device Configuration
Product Details
The MAX5857 high-performance, interpolating and modulating, 16-bit, 5.9Gsps RF DAC can directly synthesize up to 1.2GHz of instantaneous bandwidth from DC to frequencies greater than 2.6GHz. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators including DOCSIS 3.1/3.0, DVB-C2, DVB-T2, DVB-S2X, ISDB-T, and EPoC.
The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL+VCO and a 14-bit RF DAC core. The 4x linear phase interpolation filter simplifies reconstruction filtering, while enhancing passband dynamic performance and reducing the input data bandwidth required from an FPGA. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis. The complex data path can be bypassed to access the RF DAC core directly.
The MAX5857 input interface accepts 16-bit input data through a six-lane JESD204B SerDes data input interface that is Subclass-0. The interface can be configured for 3, 4, 5, or 6 lanes and supports data rates up to 9.8304Gbps to optimize the I/O lane count and speed.
The MAX5857 clock input has a flexible interface that accepts a differential sine-wave or square-wave input clock signal up to 5.9GHz. A bypassable clock multiplying PLL and VCO can be used to internally generate the high-frequency sampling clock using a reference frequency between 245.76MHz and 1.475GHz. The device provides a divided reference clock to ensure synchronization between the data source and the DAC.
The integrated RF DAC uses a differential current-steering architecture that includes a differential 50Ω internal termination and can produce a 3.2dBm full-scale output signal level on a 50Ω external load. Operating from 1.0V and 1.8V power supplies, the device consumes 2.7W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).
Applications
- Digital Video Broadcast Modulators
- DOCSIS 3.1 Remote PHY and CCAP
- DVB-C2/DVB-T2/DVB-S2X/ISDB-T
- Ethernet PON over Coax (EPoC)
- Instrumentation
- Point-to-Point Wireless
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At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.