MAX5857

LAST TIME BUY

16-Bit, 5.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface

Direct RF Synthesis of 1200MHz Instantaneous Bandwidth from DC to Greater than 2.6GHz

Data Sheet (Rev. 1) Product Selection Table

Part Models: 1
1ku List Price: price unavailable

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Overview

Simplifies RF Design and Enables New Communication Architectures
- Eliminates I/Q Imbalance and LO Feedthrough
- Enables Multi-Band RF Modulation
Direct RF Synthesis of 1.2GHz Bandwidth
- 5.898Gsps DAC Output Update Rate
- High-Performance 14-Bit RF DAC Core
- Digital Baseband I/Q with 4x Interpolation
- Bypass Path Without Interpolation for Real RF
- Digital Quadrature Modulator+NCO for Full Agility
- Sub-1Hz NCO Resolution
- Integrated Clock Multiplying PLL+VCO
Highly Flexible and Configurable
- 3, 4, 5, or 6-Lane JESD204B Input Data Interface
- Subclass-0 Compliant
- Up to 9.8304Gbps Per Lane
- Divided Reference Clock Output
- SPI Interface for Device Configuration

The MAX5857 high-performance, interpolating and modulating, 16-bit, 5.9Gsps RF DAC can directly synthesize up to 1.2GHz of instantaneous bandwidth from DC to frequencies greater than 2.6GHz. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators including DOCSIS 3.1/3.0, DVB-C2, DVB-T2, DVB-S2X, ISDB-T, and EPoC.

The device integrates interpolation filters, a digital quadrature modulator, a numerically controlled oscillator (NCO), clock multiplying PLL+VCO and a 14-bit RF DAC core. The 4x linear phase interpolation filter simplifies reconstruction filtering, while enhancing passband dynamic performance and reducing the input data bandwidth required from an FPGA. The NCO allows for fully agile modulation of the input baseband signal for direct RF synthesis. The complex data path can be bypassed to access the RF DAC core directly.

The MAX5857 input interface accepts 16-bit input data through a six-lane JESD204B SerDes data input interface that is Subclass-0. The interface can be configured for 3, 4, 5, or 6 lanes and supports data rates up to 9.8304Gbps to optimize the I/O lane count and speed.

The MAX5857 clock input has a flexible interface that accepts a differential sine-wave or square-wave input clock signal up to 5.9GHz. A bypassable clock multiplying PLL and VCO can be used to internally generate the high-frequency sampling clock using a reference frequency between 245.76MHz and 1.475GHz. The device provides a divided reference clock to ensure synchronization between the data source and the DAC.

The integrated RF DAC uses a differential current-steering architecture that includes a differential 50Ω internal termination and can produce a 3.2dBm full-scale output signal level on a 50Ω external load. Operating from 1.0V and 1.8V power supplies, the device consumes 2.7W at 4.9Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).

Applications

Digital Video Broadcast Modulators
DOCSIS 3.1 Remote PHY and CCAP
DVB-C2/DVB-T2/DVB-S2X/ISDB-T
Ethernet PON over Coax (EPoC)
Instrumentation
Point-to-Point Wireless

Part Models: 1
1ku List Price: price unavailable

Documentation

Data Sheet 1

MAX5857: 16-Bit, 5.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface Data Sheet (Rev.1) 08/20/2019

Technical Articles 1

Dissecting the Truth of RF DAC Resolution; Is It 14 or 16 Bits? 02/13/2020

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
MAX5857EXE+	144-CSP_BGA-10X10X1.17	Material Declaration Reliablity Data Package Resources	Ultra Librarian SamacSys

This is the most up-to-date revision of the Data Sheet.

Software Resources

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Hardware Ecosystem

Parts	Product Life Cycle	Description
Digital to Analog Converters (DACs) 3
MAX5869	NOT RECOMMENDED FOR NEW DESIGNS	16-Bit, 5.9Gsps Interpolating and Modulating RF DAC with JESD204B Interface
MAX5850	Obsolete	14-Bit 3.072Gsps RF DAC
MAX5855	LAST TIME BUY	16-Bit, 4.9Gsps Wideband Interpolating and Modulating RF DAC with JESD204B Interface
Phase-Locked Loop (PLL) Synthesizers 1
MAX2871	PRODUCTION	23.5MHz to 6000MHz Fractional/Integer-N Synthesizer/VCO

Tools & Simulations

Software Development 1

MAX5857 Evaluation Kit Software 1.1.1, 1.1.1

Evaluation Kits

Evaluation Kit for the MAX5857

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Features and Benefits

Evaluates the MAX5857 RF DAC Performance, Capability, and Feature Set
Single 3.3V Input Voltage Supply
Direct Interface with Xilinx VC707 Data Source Board
Windows 7/10-compatible Software
Optional On-Board SPI Interface Control for the MAX5857
On-Board SMBus™ Interface Control for the MAX6654 Temperature Sensor
Integrated GUI Controls for VC707 Operation
Proven 10-Layer PCB Design
Fully Assembled and Tested

Product Details

The MAX5857 evaluation kit (EV Kit) contains a single MAX5857 wideband interpolating and modulating RF digital-to-analog converter (DAC) which can directly synthesize 1.2GHz of instantaneous bandwidth from DC to frequencies greater than 2.6GHz. The MAX5857 EV kit provides a complete system for evaluating MAX5857 performance, as well as developing an FPGA plus DAC transmitter solution.

The MAX5857 accepts input data through a six-lane JESD204B serializer/deserializer (SerDes) interface up to 9.8304Gbps that is Subclass-0 compliant. The MAX5857 EV kit connects to one FMC connector on the Xilinx VC707 evaluation kit, allowing the VC707 to communicate with the MAX5857’s JESD204B serial link interface.

The evaluation kit includes Windows^® 7/10-compatible software that provides a simple graphical user interface (GUI) for configuration of all the MAX5857 registers through the SPI interface, control of the VC707 FPGA and temperature monitoring.