Features and Benefits

  • Direct IF Sampling Up to 400MHz
  • Excellent Dynamic Performance
    • 74.1dB/72.5dB SNR at fIN = 70MHz/175MHz
    • 83.4dBc/79.5dBc SFDR at fIN = 70MHz/175MHz
  • 3.3V Low-Power Operation
    • 637mW (Differential Clock Mode)
    • 610mW (Single-Ended Clock Mode)
  • Fully Differential or Single-Ended Analog Input
  • Adjustable Differential Analog Input Voltage
  • 750MHz Input Bandwidth
  • Adjustable, Internal or External, Shared Reference
  • Differential or Single-Ended Clock
  • Accepts 25% to 75% Clock Duty Cycle
  • User-Selectable DIV2 and DIV4 Clock Modes
  • Power-Down Mode
  • CMOS Outputs in Two's Complement or Gray Code
  • Out-of-Range and Data-Valid Indicators
  • Small, 68-Pin Thin QFN Package
  • 12-Bit Compatible Version Available (MAX12527)
  • Evaluation Kit Available (Order MAX12557 EV Kit)

Product Details

The MAX12557 is a dual 3.3V, 14-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12557 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 610mW while delivering a typical 72.5dB signal-to-noise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12557 features a 166µW powerdown mode to conserve power during idle periods.

A flexible reference structure allows the MAX12557 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from ±0.35V to ±1.15V. The MAX12557 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits.

The MAX12557 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE).

The MAX12557 features two parallel, 14-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two's complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12557 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40°C to +85°C) temperature range.

See a parametric table of the complete family of pin-compatible, 12-/14-bit high-speed ADCs.


  • Digital Set-Top Boxes
  • I/Q Receivers
  • IF and Baseband Communication Receivers: Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN
  • Low-Power Data Acquisition
  • Portable Instrumentation
  • Ultrasound and Medical Imaging

Product Lifecycle icon-recommended Production

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

Evaluation Kits (7)

Tools & Simulations

IBIS Models

Product Recommendations

MAX12557 Companion Parts

Recommended Related Parts

Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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Evaluation Boards

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.