HMC434
Info : RECOMMENDED FOR NEW DESIGNS
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HMC434

0.2 GHz to 8 GHz, GaAs, HBT MMIC, Divide by 8 Prescaler

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Models 6
1ku List Price
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Features
  • Ultralow SSB phase noise: −150 dBc/Hz typical
  • Single-ended input/outputs
  • Output power: −2 dBm typical
  • Single supply operation: 3 V
  • Ultrasmall, surface-mount, 2.90 mm × 2.80 mm, 6-lead SOT-23 package
    HMC434-EP supports defense and aerospace applications (AQEC standard)
    • Download the HMC434-EP data sheet (pdf)
    • Military temperature range (−55°C to +105°C)
    • Controlled manufacturing baseline
    • One assembly/test site
    • One fabrication site
    • Enhanced product change notification
    • Qualification data available on request
    • V62/16609 DSCC Drawing Number
Additional Details
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The HMC434 is a low noise, static, divide by 8 prescaler monolithic microwave integrated circuit (MMIC) utilizing indium gallium phosphide/gallium arsenide (InGaP/GaAs) heterojunction bipolar transistor (HBT) technology in an ultrasmall surface-mount 6-lead SOT-23 package.

The HMC434 operates from near dc (square wave) or 200 MHz (sine wave) to 8 GHz input frequency with a single 3 V dc supply.

The HMC434 features single-ended inputs and outputs for reduced component count and cost. The low additive single sideband (SSB) phase noise of −150 dBc/Hz at 100 kHz offset helps the user maintain optimal system noise performance.

Applications

  • DC to C band PLL prescalers
  • Very small aperture terminal (VSAT) radios
  • Unlicensed national information infrastructure (UNII) and point to point radios
  • IEEE 802.11a and high performance radio local area network (HiperLAN) WLAN
  • Fiber optics
  • Cellular/3G infrastructure
Part Models 6
1ku List Price
price unavailable

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Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
HMC434
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HMC434E
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HMC434ETR
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HMC434SRJZ-EP-PT
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HMC434SRJZ-EP-R7
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HMC434TR
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Software & Part Ecosystem

Evaluation Kits 2

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DC1075B

Clock Divider/Sine Wave 50Ω to CMOS Level Converter

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DC1075B

Clock Divider/Sine Wave 50Ω to CMOS Level Converter

Clock Divider/Sine Wave 50Ω to CMOS Level Converter

Product Detail

Demonstration circuit 1075B is a divide by 2/4/8 clock divider for use with high speed ADCs. Each assembly includes a clock divider followed by a re-timing stage used to produce sharp clock edges. Functionally, the DC1075B receives a high frequency sine wave which is attenuated and routed into the clock divider. The output of the clock divider is then routed to a D flip flop re-timing stage. This D flip flop is clocked by the original high frequency sine wave. This is critical to ensure signal integrity. The output of this re-timing stage is a CMOS signal suitable to be a clock source for high speed ADCs.

This circuit also is a model for designs involving FPGAs which serve as clock dividers. Whenever this is done, a D flip flop re-timing stage is required to ensure a low jitter clock signal.

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EVAL-HMC434

HMC434 Evaluation Board

Tools & Simulations 1

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