HMC432 Data Sheet4/22/2015
Features and Benefits
- Ultra Low SSB Phase Noise: -148 dBc/Hz
- Single-Ended I/O’s
- Output Power: -3 to -9 dBm
- Single DC Supply: +3V @ 42 mA
- 9 mm² Ultra Small Package: SOT26
The HMC432(E) is a low noise Divide-by-2 Static Divider utilizing InGaP GaAs HBT technology in ultra small surface mount SOT26 plastic package. This device operates from DC (with a square wave input) to 8 GHz input frequency with a single +3V DC supply. Single-ended inputs and outputs reduce component count and cost. The low additive SSB phase noise of -148 dBc/Hz at 100 kHz offset helps the user maintain good system noise performance.
- UNII, Point-to-Point & VSAT Radios
- 802.11a & HiperLAN WLAN
- Fiber Optic
- Cellular/3G Infrastructure
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (2)
This page contains ordering information for evaluating the HMC432.
The design files link includes the BOM, schematics, and Gerber files for the evaluation board.
Demonstration circuit 1075B is a divide by 2/4/8 clock divider for use with high speed ADCs. Each assembly includes a clock divider followed by a re-timing stage used to produce sharp clock edges. Functionally, the DC1075B receives a high frequency sine wave which is attenuated and routed into the clock divider. The output of the clock divider is then routed to a D flip flop re-timing stage. This D flip flop is clocked by the original high frequency sine wave. This is critical to ensure signal integrity. The output of this re-timing stage is a CMOS signal suitable to be a clock source for high speed ADCs.
This circuit also is a model for designs involving FPGAs which serve as clock dividers. Whenever this is done, a D flip flop re-timing stage is required to ensure a low jitter clock signal.
Documentation & Resources
DC1075B Demo Manual (Rev. 0)5/20/2019
Semiconductor Qualification Test Report: GaAs HBT-A (QTR: 2013-00228)10/29/2015
Package/Assembly Qualification Test Report: Plastic Encapsulated SOT26 (QTR: 02017 REV: 01)4/22/2015
PCN: MS, QS, SOT, SOIC Packages - Sn/Pb Plating Vendor Change1/17/2014
HMC Legacy PCN: SOT26 and SOT26E packages - Relocation of pre-existing production equipment to new building2/1/2013
SOT 26 Tape Specification11/3/2015
Tools & Simulations
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|HMC432||Material Declaration||Reliability Data||6-Lead SOT-23|
|HMC432E||Material Declaration||Reliability Data||6-Lead SOT-23|
|HMC432ETR||Material Declaration||Reliability Data||6-Lead SOT-23|
|HMC432TR||Material Declaration||Reliability Data||6-Lead SOT-23|
|Wafer Fabrication Data|
Support & Discussions
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.