ADSP-TS201S
500/600 MHz TigerSHARC Processor with 24 Mbit on-chip embedded DRAM
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BSDL Model File
ADSP-TS20x TigerSHARC BSDL File 25x25mm PBGA Package for Revision 1.2, (03/2005)
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BSDL Model File
ADSP-TS20x TigerSHARC BSDL File 25x25mm PBGA Package for Revision 1.1, (03/2005)
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IBIS Model
ADSP-TS201S IBIS Datafile BGA Package (09/2003)
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Features
- Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
- High performance up to 600 MHz, 1.67 ns instruction rate DSP core
- 24 Mbit on-chip embedded DRAM internally organized in six banks with user-defined partitioning
- Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC Processor to offer complete baseband processing
- 14 channel, zero overhead DMA controller
- Four internal 128-bit wide internal buses providing a total memory bandwidth of 38.4 Gbytes per second
- Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
- Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
- Assembly and C language programmability
- Temperature range -40°C to +85°C
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The ADSP-TS201S is one of the members of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI's TigerSHARC Processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS201S features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC Processor to offer unrivaled DSP performance. At a 600 MHz clock rate, the ADSP-TS201S offers the industry's highest 16-bit fixed-point and 32-bit floating point performance. The ADSP-TS201S has a 1024-point complex FFT time of 16.8 microseconds and provides 1500 MFLOPs per watt.
ADSP-TS201S Performance:
- High performance 600 MHz, 1.67 ns instruction rate DSP core
- Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle
- Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (3.6 GFLOPS or 14.4 GOPS performance)
- 2-cycle, interlocked execution pipe
- Parallelism allows the execution of up to four 32-bit instructions per cycle
The ADSP-TS201S is available in a 25x25mm inexpensive, BGA package. The TigerSHARC Processor is available for general purpose sampling today.
4
B
BSDL Model File
ADSP-TS20x TigerSHARC BSDL File 25x25mm PBGA Package for Revision 1.2, (03/2005)
B
BSDL Model File
ADSP-TS20x TigerSHARC BSDL File 25x25mm PBGA Package for Revision 1.1, (03/2005)
B
IBIS Model
ADSP-TS201S IBIS Datafile BGA Package (09/2003)
B
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Search
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
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ADSP-TS201S
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Application Note
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306 kB
Obsolete Data Sheet
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Legacy Emulator Manual
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Documentation
User Guide 1
Application Note 25
AN-911: A Detailed Guide to Powering the TigerSHARC Processors (Rev.0)
EE-211: 16-bit FIR Filters on ADSP-TS20x TigerSHARC® Processors (Rev.1)
EE-110: A Quick Primer on ELF and DWARF File Formats
EE-215: A 16-bit IIR Filter on the ADSP-TS20x TigerSHARC® Processor
EE-205: Considerations for Porting Code from the ADSP-TS101S TigerSHARC® Processor to the ADSP-TS201S TigerSHARC Processor
EE-283: External Bus Arbitration with ADSP-TS20x TigerSHARC® Processors (Rev.1)
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++
EE-170: Estimating Power for ADSP-TS201S TigerSHARC® Processors (Rev.2)
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)
EE-218: Writing Efficient Floating-Point FFTs for ADSP-TS201 TigerSHARC® Processors (Rev.2)
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)
EE-147: Tuning C Source Code for the TigerSHARC® DSP Compiler
EE-198: User Guide to ADSP-TS201S TigerSHARC® Processor IBIS Files
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)
EE-182: Thermal Relief Design for ADSP-TS201S TigerSHARC® Processors (Rev.1)
EE-263: Parallel Implementation of Fixed-Point FFTs on TigerSHARC® Processors (Rev.1)
EE-210: SDRAM Selection and Configuration Guidelines for ADI Processors (Rev.2)
EE-104: Setting Up Streams with the VisualDSP Debugger
EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev.1)
EE-167: Introduction to TigerSHARC® Multiprocessor Systems Using VisualDSP++™
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)
EE-201: ADSP-TS20x TigerSHARC® Processor On-chip SDRAM Controller (Rev.1)
EE-200: ADSP-TS20x TigerSHARC® Processor Boot Loader Kernels Operation (Rev.1)
EE-179: ADSP-TS20xS TigerSHARC® System Design Guidelines (Rev.6)
Technical Articles 1
Processor Manual 3
Product Highlight 2
Software Manual 10
VisualDSP++® 5.0 Users Guide (Rev.3.0)
VisualDSP++® 5.0 Quick Installation Reference Card (Rev.3.1)
VisualDSP++® 5.0 Licensing Guide (Rev.1.4)
VisualDSP++® 5.0 Loader and Utilities Manual (Rev.2.5)
VisualDSP++® 5.0 Product Release Bulletin (Rev.3.0)
VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev.3.4)
VisualDSP++® 5.0 Getting Started Guide (Rev.3.0)
VisualDSP++® 5.0 C/C++ Compiler and Library Manual for TigerSHARC Processors (Rev.4.1)
VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev.3.5)
VisualDSP++® 5.0 Linker and Utilities Manual (Rev.3.5)
Integrated Circuit Anomaly 1
Legacy Emulator Manual 1
Informational 1
Obsolete Data Sheet 1
Legacy Evaluation Kit Manual 3
Product Highlight 2
Product Selection Guide 1
Software & Part Ecosystem
Code Examples
Looking for Evaluation Software? You can find it here
Evaluation Kits 2
EMULATOR-USB & HP USB ICE
USB-Based Emulator and High Performance USB-Based Emulator
Features and Benefits
- Full speed USB 1.1 interface enabling download speeds of up to 150 KB/Sec (ADZS-USB-ICE) or High speed USB 2.0 interface enabling download speeds of up to 1.5MB/sec (ADZS-HPUSB-ICE)
- Background Telemetry Channel (BTC) support enabling non-intrusive data exchange at up to 2.0 MB/sec (ADZS-HPUSB-ICE only)
- 1.8V, 2.5V, and 3.3V compliant and tolerant
- Support for all ADI JTAG processors and DSPs
- 5V tolerant and 3.3V compliant for 5V processors and DSPs
- Multiprocessor support
- 14-pin JTAG connector
- 3-meter USB cable for difficult-to-reach targets
- CE-certified
Product Detail
The plug-and-play architecture of USB allows the emulators to be automatically detected and configured by the host operating system. It can also be connected to and disconnected from the host without opening the PC or turning off the power to the PC. A 3-meter cable is included to connect the emulators to the host PC, thus providing abundant accessibility to hard to reach targets.
The HP USB-based emulator also supports the Background
Telemetry Channel (BTC), a non-intrusive method
for exchanging data between the host and target
application without affecting the target system's
real-time characteristics.
Part Number:
USB-Based Emulator
Part Number: ADZS-USB-ICE
High Performance USB-Based Emulator
Part Number: ADZS-HPUSB-ICE
Tools Support:
Tel: 1-800-ANALOGD (262-5643)
Contact Support
For additional information, contact your local Analog Devices Sales Office or Distributor.
Resources
EVAL-TS201S-EZKIT
EZ-KIT Lite Evaluation Kit for ADSP-TS201S Processor
Features and Benefits
- Dual ADSP-TS201S TigerSHARC® Processors
- 4 Mb (512K x 8-bit) FLASH memory
- 32 MB (4M x 64-bit) SDRAM
- AD1871 stereo, 24-bit, 96 kHz, multi-bit Sigma-Delta ADC
- AD1854 stereo, 24-bit, 96 kHz, multi-bit Sigma-Delta DAC
- Two 1/8” stereo audio jacks
- 4 external LVDS link port connectors (1 Transmit and 1 Receive per processor)
Product Detail
The EZ-KIT Lite’s default EPROM boot mode enables the board to be used as a standalone unit without the requirement for a PC-host. If desired, the board can boot from an optional external host port interface connector, link port or “No Boot” based on jumper selections. The EZ-KIT Lite also includes a FLASH utility that can be used to download user specific boot code to the on-board FLASH memory using the USB interface
Part Number: ADZS-TS201S-EZLITE
Tools Support::
Tel: 1-800-ANALOGD (262-5643)
Contact Support
Resources
Tools & Simulations 3
BSDL Model File 4
BSDL Model File
IBIS Model 1
TigerSHARC Processors: Software and Tools
