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  5. ADSP-TS101S

Data Sheet Rev. E
User Guides Rev. 2.1
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Code Examples
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Overview

Features and Benefits

  • 300 MHz, 3.3 ns instruction cycle rate
  • 6M bits of internal—on-chip—SRAM memory
  • 19 mm × 19 mm (484-ball) CSP_BGA or 27 mm× 27 mm (625-ball) PBGA package
  • Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
  • Dual integer ALUs, providing data addressing and pointer manipulation
  • Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin for system integration
  • 1149.1 IEEE compliant JTAG test access port for on-chip emulation
  • On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus
  • Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications
  • Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2 in the data sheet)
  • Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors
  • Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture
  • Enables scalable multiprocessing systems with low communications overhead

Product Details

The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static Superscalar™ processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Three independent 128-bit-wide internal data buses, each connecting to one of the three 2M bit memory banks, enable quad word data, instruction, and I/O accesses and provide 14.4G bytes per second of internal memory bandwidth. Operating at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS101S can perform 2.4 billion 40-bit MACs or 600 million 80-bit MACs per second. Table 1 and Table 2 in the data sheet show the DSP’s performance benchmarks.

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Evaluation Kits (2)

Documentation & Resources

  • View All (41)
  • Data Sheets (1)
  • Application Notes (20)
  • User Guides (1)
  • Processor Manuals (3)
  • Software Manuals (10)
  • Integrated Circuit Anomalies (1)
  • Legacy Emulator Manuals (2)
  • Product Highlight (1)
  • Product Selection Guide (1)
  • Technical Articles (1)
    • Document Type
    Application Notes
    Software Manuals

    Software & Systems Requirements

    Code Examples

    TigerSHARC Processor Code Examples

    Evaluation Software

    TigerSHARC Evaluation Kits

    Tools & Simulations

    IBIS Models

    ZIP
    ADSP-TS101S IBIS Datafile BGA Package

    [IBIS Ver]2.1, [File Rev]2.4,[Date]10/27/03

    Design Tools

    BSDL Model Files

    Designing with BGA

    Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages

    Design Resources

    ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.

    Part Number Material Declaration Reliability Data Pin/Package Drawing CAD Symbols, Footprints & 3D Models
    ADSP-TS101SAB1Z000 Material Declaration Reliability Data 625 ball BGA
    ADSP-TS101SAB1Z100 Material Declaration Reliability Data 625 ball BGA
    ADSP-TS101SAB2Z000 Material Declaration Reliability Data 484 ball BGA
    ADSP-TS101SAB2Z100 Material Declaration Reliability Data 484 ball BGA
    Wafer Fabrication Data

    PCN-PDN Information

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    Select Model for PCN Information
    • ADSP-TS101SAB1Z000 Production
    • ADSP-TS101SAB1Z100 Production
    • ADSP-TS101SAB2Z000 Production
    • ADSP-TS101SAB2Z100 Production

    Support & Discussions

    ADSP-TS101S Discussions

    Problem with TS101 in emulation mode
    Hardware Design Checklist for ADSP-TS201S TigerSHARC® Processors
    All ADSP-TS101S Discussions
    ADSP-TS101S Contact ADI Technical Support »
    ADSP-TS101S Ask your question »
    ADSP-TS101S Contact ADI Technical Support » ADSP-TS101S Ask your question »

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