ADSP-TS101S
Info: : PRODUCTION
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ADSP-TS101S

300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

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Info: : PRODUCTION tooltip
Part Details
Features
  • 300 MHz, 3.3 ns instruction cycle rate
  • 6M bits of internal—on-chip—SRAM memory
  • 19 mm × 19 mm (484-ball) CSP_BGA or 27 mm× 27 mm (625-ball) PBGA package
  • Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
  • Dual integer ALUs, providing data addressing and pointer manipulation
  • Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin for system integration
  • 1149.1 IEEE compliant JTAG test access port for on-chip emulation
  • On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus
  • Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications
  • Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2 in the data sheet)
  • Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors
  • Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture
  • Enables scalable multiprocessing systems with low communications overhead
Additional Details
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The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static Superscalar processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

Three independent 128-bit-wide internal data buses, each connecting to one of the three 2M bit memory banks, enable quad word data, instruction, and I/O accesses and provide 14.4G bytes per second of internal memory bandwidth. Operating at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS101S can perform 2.4 billion 40-bit MACs or 600 million 80-bit MACs per second. Table 1 and Table 2 in the data sheet show the DSP’s performance benchmarks.

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADSP-TS101SAB1Z000
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ADSP-TS101SAB1Z100
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Product Lifecycle

PCN

Aug 23, 2023

- 23_0004

Assembly Site Transfer of Select PBGA Products to ASE Kaohsiung (AEG)

Jul 14, 2021

- 20_0165

Assembly Transfer of Select PBGA Products to ASE Chungli (AET)

Jun 18, 2010

- 07_0093

Conversion to Laser Mark for all ADSPXXXX, ADSSTXXXX, and PC Audio Codecs Ink on Plastic Encapsulated Parts

ADSP-TS101SAB1Z000

PRODUCTION

ADSP-TS101SAB1Z100

PRODUCTION

Apr 17, 2012

- 12_0047

Ink-to-Laser Mark Conversion for the CSP_BGA and PBGA Packages (for Post-test Multi-grade parts)

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Aug 23, 2023

- 23_0004

arrow down

Assembly Site Transfer of Select PBGA Products to ASE Kaohsiung (AEG)

Jul 14, 2021

- 20_0165

arrow down

Assembly Transfer of Select PBGA Products to ASE Chungli (AET)

Jun 18, 2010

- 07_0093

arrow down

Conversion to Laser Mark for all ADSPXXXX, ADSSTXXXX, and PC Audio Codecs Ink on Plastic Encapsulated Parts

ADSP-TS101SAB1Z000

PRODUCTION

ADSP-TS101SAB1Z100

PRODUCTION

Apr 17, 2012

- 12_0047

arrow down

Ink-to-Laser Mark Conversion for the CSP_BGA and PBGA Packages (for Post-test Multi-grade parts)

Evaluation Kit

Evaluation Kits 2

reference details image

EMULATOR-USB & HP USB ICE

USB-Based Emulator and High Performance USB-Based Emulator

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EMULATOR-USB & HP USB ICE

USB-Based Emulator and High Performance USB-Based Emulator

USB-Based Emulator and High Performance USB-Based Emulator

Features and Benefits

  • Full speed USB 1.1 interface enabling download speeds of up to 150 KB/Sec (ADZS-USB-ICE) or High speed USB 2.0 interface enabling download speeds of up to 1.5MB/sec (ADZS-HPUSB-ICE)
  • Background Telemetry Channel (BTC) support enabling non-intrusive data exchange at up to 2.0 MB/sec (ADZS-HPUSB-ICE only)
  • 1.8V, 2.5V, and 3.3V compliant and tolerant
  • Support for all ADI JTAG processors and DSPs
  • 5V tolerant and 3.3V compliant for 5V processors and DSPs
  • Multiprocessor support
  • 14-pin JTAG connector
  • 3-meter USB cable for difficult-to-reach targets
  • CE-certified

Product Detail

Analog Devices’ cost-effective Universal Serial Bus (USB)-based emulator and High performance (HP) Universal Serial Bus (USB)-based emulator each provide an easy, portable, non-intrusive, target-based debugging solution for Analog Devices JTAG processors and DSPs. These powerful USB-based emulators perform a wide range of emulation functions, including single-step and full speed execution with pre-defined breakpoints, and viewing and/or altering of register and memory contents. With the ability to automatically detect and support multiple I/O voltages, the USB and HP USB emulators enable users to communicate with all of the Analog Devices JTAG processors and DSPs using either a full speed USB 1.1 or high speed USB 2.0 port on the host PC. Applications and data can easily and rapidly be tested and transferred between the emulators and the separately available VisualDSP++ development and debugging environment(sold separately).

The plug-and-play architecture of USB allows the emulators to be automatically detected and configured by the host operating system. It can also be connected to and disconnected from the host without opening the PC or turning off the power to the PC. A 3-meter cable is included to connect the emulators to the host PC, thus providing abundant accessibility to hard to reach targets.

The HP USB-based emulator also supports the Background Telemetry Channel (BTC), a non-intrusive method for exchanging data between the host and target application without affecting the target system's real-time characteristics.

Part Number:
USB-Based Emulator
Part Number: ADZS-USB-ICE
High Performance USB-Based Emulator
Part Number: ADZS-HPUSB-ICE

Tools Support:
Tel: 1-800-ANALOGD (262-5643)
Contact Support

For additional information, contact your local Analog Devices Sales Office or Distributor.

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EVAL-TS201S-EZKIT

EZ-KIT Lite Evaluation Kit for ADSP-TS201S Processor

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EVAL-TS201S-EZKIT

EZ-KIT Lite Evaluation Kit for ADSP-TS201S Processor

EZ-KIT Lite Evaluation Kit for ADSP-TS201S Processor

Features and Benefits

  • Dual ADSP-TS201S TigerSHARC® Processors
  • 4 Mb (512K x 8-bit) FLASH memory
  • 32 MB (4M x 64-bit) SDRAM
  • AD1871 stereo, 24-bit, 96 kHz, multi-bit Sigma-Delta ADC
  • AD1854 stereo, 24-bit, 96 kHz, multi-bit Sigma-Delta DAC
  • Two 1/8” stereo audio jacks
  • 4 external LVDS link port connectors (1 Transmit and 1 Receive per processor)

Product Detail

The ADSP-TS201S EZ-KIT Lite provides developers with a cost-effective method for initial evaluation of the ADSP-TS201S TigerSHARC® Processor and its multiprocessing capabilities. This EZ-KIT Lite includes two ADSP-TS201S processors on a desktop evaluation board along with fundamental debugging software to facilitate architecture evaluations via a USB-based PC-hosted tool set. With this EZ-KIT Lite, users can learn more about ADI’s ADSP-TS201S hardware and software development environments and quickly prototype applications. The ADSP-TS201S EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Via the USB interface, VisualDSP++ can communicate with the included software debug agent enabling users to perform standard debugging functions (such as read and write memory, read and write registers, load and execute executables, set and clear breakpoints, and single-step assembly, C, and C++ source code) and multiprocessor functions (such as synchronous step, synchronous run, and synchronous halt). The evaluation versions of the included software tools have limited use with the EZ-KIT Lite.

The EZ-KIT Lite’s default EPROM boot mode enables the board to be used as a standalone unit without the requirement for a PC-host. If desired, the board can boot from an optional external host port interface connector, link port or “No Boot” based on jumper selections. The EZ-KIT Lite also includes a FLASH utility that can be used to download user specific boot code to the on-board FLASH memory using the USB interface


Part Number: ADZS-TS201S-EZLITE


Tools Support:: Tel: 1-800-ANALOGD (262-5643)
Contact Support

Tools & Simulations

Tools & Simulations 3

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