ADSP-TS101S
PRODUCTION300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM
- Part Models
- 2
- 1ku List Price
- price unavailable
Part Details
- 300 MHz, 3.3 ns instruction cycle rate
- 6M bits of internal—on-chip—SRAM memory
- 19 mm × 19 mm (484-ball) CSP_BGA or 27 mm× 27 mm (625-ball) PBGA package
- Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
- Dual integer ALUs, providing data addressing and pointer manipulation
- Integrated I/O includes 14-channel DMA controller, external port, 4 link ports, SDRAM controller, programmable flag pins, 2 timers, and timer expired pin for system integration
- 1149.1 IEEE compliant JTAG test access port for on-chip emulation
- On-chip arbitration for glueless multiprocessing with up to 8 TigerSHARC processors on a bus
- Provides high performance Static Superscalar DSP operations, optimized for telecommunications infrastructure and other large, demanding multiprocessor DSP applications
- Performs exceptionally well on DSP algorithm and I/O benchmarks (see benchmarks in Table 1 and Table 2 in the data sheet)
- Supports low overhead DMA transfers between internal memory, external memory, memory-mapped peripherals, link ports, other DSPs (multiprocessor), and host processors
- Eases DSP programming through extremely flexible instruction set and high-level language-friendly DSP architecture
- Enables scalable multiprocessing systems with low communications overhead
The ADSP-TS101S TigerSHARC® processor is an ultrahigh performance, Static Superscalar™ processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.
Three independent 128-bit-wide internal data buses, each connecting to one of the three 2M bit memory banks, enable quad word data, instruction, and I/O accesses and provide 14.4G bytes per second of internal memory bandwidth. Operating at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns instruction cycle time. Using its single-instruction, multiple-data (SIMD) features, the ADSP-TS101S can perform 2.4 billion 40-bit MACs or 600 million 80-bit MACs per second. Table 1 and Table 2 in the data sheet show the DSP’s performance benchmarks.
Documentation
Data Sheet 1
User Guide 1
Application Note 20
Technical Articles 1
Processor Manual 3
Product Highlight 1
Software Manual 10
Integrated Circuit Anomaly 1
Legacy Emulator Manual 2
Legacy Evaluation Kit Manual 1
Product Highlight 1
Product Selection Guide 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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ADSP-TS101SAB1Z000 | 625 ball BGA | ||
ADSP-TS101SAB1Z100 | 625 ball BGA |
Part Models | Product Lifecycle | PCN |
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Aug 23, 2023 - 23_0004 Assembly Site Transfer of Select PBGA Products to ASE Kaohsiung (AEG) |
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ADSP-TS101SAB1Z000 | ||
ADSP-TS101SAB1Z100 | ||
Jul 14, 2021 - 20_0165 Assembly Transfer of Select PBGA Products to ASE Chungli (AET) |
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ADSP-TS101SAB1Z000 | ||
ADSP-TS101SAB1Z100 | ||
Jun 18, 2010 - 07_0093 Conversion to Laser Mark for all ADSPXXXX, ADSSTXXXX, and PC Audio Codecs Ink on Plastic Encapsulated Parts |
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ADSP-TS101SAB1Z000 | ||
ADSP-TS101SAB1Z100 | ||
Apr 17, 2012 - 12_0047 Ink-to-Laser Mark Conversion for the CSP_BGA and PBGA Packages (for Post-test Multi-grade parts) |
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ADSP-TS101SAB1Z100 |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Code Examples 1
Evaluation Software 1
Tools & Simulations
BSDL Model File 6
- ADSP-TS101: 27x27 PBGA Package Siicon Revision 0.2, [BSDL Original File], 09/09/2003
- ADSP-TS101: 19x19mm PBGA Silicon Revision 0.0 and 0.1 [BSDL Original File], 02/08/2001
- ADSP-TS101: 27x27 PBGA Package Silicon Revision 0.0 and 0.1 [BSDL Original File], 10/12/2001
- ADSP-TS101 TigerSHARC BSDL File 27x27mm PBGA Package for Revision 0.4, (11/2006)
- ADSP-TS101 TigerSHARC BSDL File 19x19mm PBGA Package for Revision 0.4, (11/2006)
- ADSP-TS101: 19x19mm PBGA Package Silicon Revision 0.2, [BSDL Original File], 09/09/2003
Designing with BGA
Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages
Open ToolIBIS Model 1
TigerSHARC Processors: Software and Tools
Open Tool