Features and Benefits

  • 40MHz (25ns instruction rate) SISD SHARC Core
  • 120MFLOPs peak performance
  • Code compatible with all SHARC processors
  • Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
  • 2Mbits of on-chip dual-ported SRAM
  • Host Processor Interface
  • Six Link Ports for point to point connectivity and array multiprocessing
  • Two synchronous serial ports with independent transmit and receive functions
  • 10 Channel DMA controller
  • Glueless connection for scalable DSP multiprocessing

Product Details

The ADSP-21062 and ADSP-21060 SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

The ADSP-2106x SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062, 1 Mbit on the ADSP-21061), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

Product Lifecycle icon-not-recommended Not Recommended for New Designs

This designates products ADI does not recommend broadly for new designs.

Documentation & Resources

  • View All (47)
  • Data Sheet (1)
  • Application Note (39)
  • Processor Manual (3)
  • Integrated Circuit Anomaly (1)
  • Legacy Emulator Manual (2)
  • Technical Article (1)
  • Application Note

    Software & Systems Requirements

    Software & Tools Anomaly

    Tools & Simulations

    IBIS Model

    ADSP-21062 IBIS Datafile (BGA Package)

    [IBIS Ver]2.1, [File Rev]1.1,[Date]12/02/98

    ADSP-21062 IBIS Datafile (QFP Package)

    [IBIS Ver]2.1, [File Rev]1.1,[Date]12/02/98

    BSDL Model File

    Designing with BGA

    Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages

    ADSP-21062: PQFP (EDQUAD) package

    [BSDL Revision] 1.6, [Date] 01/08/99