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ADSP-21062

SHARC, 40 MHz, 120 MFLOPS, 5v, Floating Point

Not Recommended for New Designs

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Overview

Features and Benefits
Product Details

Features and Benefits

40MHz (25ns instruction rate) SISD SHARC Core
120MFLOPs peak performance
Code compatible with all SHARC processors
Supports IEEE-compatible 32-bit floating-point, 40-bit floating point, and 32-bit fixed point math
2Mbits of on-chip dual-ported SRAM

Glueless connection for scalable DSP multiprocessing
Six Link Ports for point to point connectivity and array multiprocessing
Two synchronous serial ports with independent transmit and receive functions
10 Channel DMA controller
Host Processor Interface

Product Details

The ADSP-21062 and ADSP-21060 SHARC DSPs are signal processing microcomputers that offer new capabilities and levels of performance. The ADSP-2106x SHARCs are 32-bit processors optimized for high performance DSP applications. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O peripherals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the ADSP-2106x has a 25 ns instruction cycle time and operates at 40 MIPS. With its on-chip instruction cache, the processor can execute every instruction in a single cycle.

The ADSP-2106x SHARC DSP represents a new standard of integration for signal computers, combining a high performance floating-point DSP core with integrated, on-chip system features including a 4 Mbit SRAM memory (2 Mbit on the ADSP-21062, 1 Mbit on the ADSP-21061), host processor interface, DMA controller, serial ports, and link port and parallel bus connectivity for glueless DSP multiprocessing.

Product Categories

Audio & Video Products
- SHARC Processors

Processors & DSP
- SHARC Processors

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Product Lifecycle Not Recommended for New Designs

This designates products ADI does not recommend broadly for new designs.

Documentation

Data Sheets (1)

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC: SHARC Processor Data Sheet (Rev. H)

Application Notes (39)

EE-112: Class Implementation in Analog C++

EE-332: Cycle Counting and Profiling (Rev. 2)

EE-332: Code example

EE-340: Connecting SHARC^® and Blackfin^® Processors over SPI (Rev. 1)

EE-340: Code example

EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)

EE-323: Associated Code

EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)

EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)

EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)

EE-175: Associated Files

EE-280: In-Circuit Flash Programming on ADSP-2106x SHARC® Processors (Rev. 2)

EE-280: Code Example (Rev 2, 03/2007)

EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)

EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)

EE-84: Code Example (Rev 2, 2/2007)

EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)

EE-305: Designing and Debugging Systems with SHARC Processors (Rev. 1)

EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)

EE-267 Software Code

EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)

EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)

EE-202 Software Code

EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1)

EE-241 Software Code

EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs

EE-191 Software Code

EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)

EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs

EE-166: ADSP-2106x EPROM Overlay Support with VisualDSP++ 2.0

EE-166 Software Code

EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports

EE-160 Software Code

EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™

EE-132 Software Code

EE-128: DSP in C++: Calling Assembly Class Member Functions From C++

EE-116: SHARC Shortword DMA

EE-116 Software Code

EE-109: ADSP2106x : Using 2106x SPORT's as Timers

EE-86: Interfacing SHARC 2106x DSPs to PLX 9080 PCI Bridge Chips

EE-85: Recommended Handling of Unused SHARC Pins

EE-70: ADSP-2106x SPORT DTx pins: Is There Potential MCM Data Contention Between Different SHARCs

EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)

EE-69: Code Example (Rev 2, 01/2007)

EE-62: Accessing Short Word Memory In C

EE-47: ADSP-2106x Link Ports - Maximum Throughput

EE-46: SHARC Internal Power Measurements

EE-45: Using the ADSP-2106x/21020 EZ-ICE DBWIN Utility

EE-42: C-Programs on the ADSP-2106x

EE-110: A Quick Primer on ELF and DWARF File Formats

EE-104: Setting Up Streams with the VisualDSP Debugger

EE-104 Software Code

EE-74: Analog Devices Serial Port Development and Troubleshooting Guide

EE-103: Performing Level Conversion Between 5v and 3.3v IC's

EE-37: How to Interface an LCD to the 21xx and 2106x Family DSP's

Processor Manuals (3)

SHARC Processors: Manuals

Getting Started with SHARC

ADSP-2106x SHARC^® User's Manual (Rev. 2.1)

Documentation Errata

Integrated Circuit Anomalies (1)

ADSP-21062/ADSP-21062L SHARC Anomaly List for Revisions 2.0, 2.1, 3.0 (Rev. A)

Legacy Emulator Manuals (2)

Apex-ICE USB Emulator Hardware Installation Guide (Rev. 6.0)

Summit-ICE PCI Emulator Hardware Installation Guide (Rev. 4)

Software & Systems Requirements

Software & Tools Anomalies

Software and Tools Anomalies Search

Tools & Simulations

IBIS Models

TXT

ADSP-21062 IBIS Datafile (BGA Package)

[IBIS Ver]2.1, [File Rev]1.1,[Date]12/02/98

TXT

ADSP-21062 IBIS Datafile (QFP Package)

[IBIS Ver]2.1, [File Rev]1.1,[Date]12/02/98

BSDL Model Files

Designing with BGA

Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages

TXT

28 kB

ADSP-21062 SHARC Processor BSDL File 225 ball PBGA Package (10/2009)

TXT

ADSP-21062: PQFP (EDQUAD) package

[BSDL Revision] 1.6, [Date] 01/08/99

Reference Materials

Technical Articles (1)

An Efficient Asynchronous Sampling-rate Conversion Algorithm for...

Analog Dialogue (1)

Floating-point DSP Leads in Performance

Design Resources

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Discussions

ADSP-21062 Discussions

RE: Are FIR/IIR Accelerators on ADSP-2156x faster than the core?

2 week(s) ago in 2156x

RE: How can we program ADSP-2156x FIR/IIR Accelerators?

2 week(s) ago in 2156x

RE: What enhancements have been done in ADSP-2156x FIR/IIR accelerators?

2 week(s) ago in 2156x

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