The ADRV9010 is a highly integrated, radio frequency (RF) agile transceiver that offers four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions to provide a complete transceiver solution. The device provides the high radio performance and low power consumption demanded by cellular infrastructure applications such as TDD-based small cell base station radios, macro 3G/4G/5G TDD systems, and TDD based massive multiple in/multiple out (MIMO) base stations. The ADRV9010BBCZ operates from 650 MHz to 3800 MHz, covering most of the licensed and unlicensed cellular bands. The ADRV9010BBCZ-A operates from 650 MHz to 6000 MHz.
The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The four independent transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise. The ADRV9010 device also includes two wide bandwidth, time shared observation path receivers with two inputs each for monitoring transmitter outputs.
The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated.
To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide high performance, low power fractional-N RF synthesis for the transmitter and receiver signal paths. One fully integrated PLL also supports an independent local oscillator (LO) mode for the observation receiver. Another PLL generates the clocks needed for the converters and digital circuits and a fifth PLL provides the clock for the serial data interface. A multichip
synchronization mechanism synchronizes the phases of all LOs and baseband clocks between multiple ADRV9010 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.
The serial data interface consists of eight serializer lanes and eight deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 16.22016 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.
The ADRV9010 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI). Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9010 is packaged in a 14 mm × 14 mm, 289-ball chip scale ball grid array (CSP_BGA).
APPLICATIONS
- 3G/4G/5G TDD macro and small cell base stations
- TDD active antenna systems for advanced LTE and 5G
