ADL5246

Obsolete

3 GHz Variable Gain LNA with Integrated ½ W Driver Amplifier

Data Sheet (Rev. A) Product Selection Table

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Part Details

RF output frequency range: 0.6 GHz to 3 GHz
Output IP3: 37 dBm at 2.2 GHz
Output P1dB: 28 dBm at 2.2 GHz
Noise figure of input amplifier: 1 dB at 2.2 GHz
Maximum gain: 31.5 dB at 2.2 GHz
Voltage variable attenuation range: 45 dB

0 V to 3.3 V attenuation control range
Integrated bypass switch for low noise VGA
Matched 50 Ω input stage
3.3 V to 5 V single supply
32-lead, 5 mm × 5 mm LFCSP package

Documentation

Data Sheet 1

ADL5246: 3 GHz Variable Gain LNA with Integrated ½ W Driver Amplifier Data Sheet (Rev.A) 05/05/2014

Technical Articles 1

High Dynamic Range IF Receiver Simplifies Design of Next-Generation μW Point-to-Point Modems 11/01/2014

This is the most up-to-date revision of the Data Sheet.

Software Resources

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Tools & Simulations

S-Parameter 1

ADL5246 S-Parameters

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

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Evaluation Kits

ADL5246 Evaluation Board

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Product Details

ADL5246-EVALZ is a fully populated, 4-layer, FR408-based evaluation board. For operation, it requires a 5 V/500 mA power supply and two 3 V/100 mA power supplies. The variable gain amplifier (AMP2) is analog controlled and the 0 V to 3.3 V gain control pins maybe operated independently or in tandem. The internal bypass switch operates with a 3.3 V complementary logic. The LNA (AMP1), VGA (AMP2), and DRIVER (AMP3) can be individually biased using the test loops labeled VCC1, VPOS1, VPOS2, VCC3 and GND. VCC1 provides bias to the LNA (AMP1). VPOS1 and VPOS2 provide the bias for the VGA (AMP2). VPOS1 provides bias for the VGA amp circuit and VPOS2 provides bias to the internal VVAs and to the bias circuit of the DRIVER (AMP3). VPOS2 and VCC3 must be connected when operating the DRIVER. VPOS1 and VPOS2 are connected to an internal power plane via R6 and R7. Removing R6 and R7 allows VPOS1 and VPOS2 to be powered separately. A fully cascaded signal chain, an LNA driving the VGA, followed by the DRIVER, can be configured using the available resistor and capacitor pads.

Resources

ADL5246 Gerber Files
3/17/2016

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