Features and Benefits

  • SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
  • SFDR = 81 dBc to 70 MHz at 150 MSPS
  • Low power: 825 mW at 150 MSPS
  • 1.8 V analog supply operation
  • Integer 1 to 8 input clock divider
  • 1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
  • Intermediate frequency (IF) sampling frequencies up to 450 MHz
  • See datasheet for additional features

Product Details

The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9600 has several functions that simplify the automated gain control (AGC) function in a communications receiver. For example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monitoring the amplitude of the incoming signal with short latency, using the four fast detect bits of the ADC. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly adjust the system gain to avoid an overrange condition.

Another AGC-related function of the AD9600 is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 10-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. In addition, flexible power-down options allow significant power savings.


  1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
  2. Fast overrange detect and signal monitor with serial output.
  3. Signal monitor block with dedicated serial output mode.
  4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 450 MHz.
  5. The AD9600 operates from a single 1.8 V supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
  6. A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down mode, and voltage reference mode.
  7. The AD9600 is pin compatible with the AD9627-11, AD9627, and AD9640, allowing a simple migration from 10 bits to 11 bits, 12 bits, or 14 bits.


  • Point-to-point radio receivers (GPSK, QAM)
  • Diversity radio systems
  • I/Q demodulation systems
  • Smart antenna systems
  • Digital predistortion
  • General-purpose software radios
  • Broadband data applications
  • Data acquisition
  • Nondestructive testing

Product Lifecycle icon-recommended Production

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.