AD9542
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AD9542

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $9.61
Features
  • Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
  • Complies with ITU-T G.8262 and Telcordia GR-253
  • Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825
  • Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb
  • Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulus
  • Programmable digital loop filter bandwidth: 10−4 Hz to 1850 Hz
  • Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operation
  • Programmable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported
  • 5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)
  • 2 differential or 4 single-ended input references
  • Crosspoint mux interconnects reference inputs to PLLs
  • Supports embedded (modulated) input/output clock signals
  • Fast DPLL locking modes
  • Provides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXO
  • External EEPROM support for autonomous initialization
  • Single 1.8 V power supply operation with internal regulation
  • Built in temperature monitor/alarm and temperature compensation for enhanced zero delay performance
Additional Details
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The 10 clock outputs of the AD9542 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.

The AD9542 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.

Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.

Applications

  • SyncE jitter cleanup and synchronization
  • Optical transport networks (OTN), SDH, and macro and small cell base stations
  • OTN mapping/demapping with jitter cleaning
  • Small base station clocking, including baseband and radio
  • Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
  • JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
  • Cable infrastructures
  • Carrier Ethernet
Part Models 2
1ku List Price Starting From $9.61

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9542BCPZ
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AD9542BCPZ-REEL7
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Product Lifecycle

PCN

Oct 3, 2022

- 22_0207

AD9542 Data Sheet Specification Revision

AD9542BCPZ

PRODUCTION

AD9542BCPZ-REEL7

PRODUCTION

Dec 13, 2018

- 18_0199

AD9542 Data Sheet Specification Changes

AD9542BCPZ

PRODUCTION

AD9542BCPZ-REEL7

PRODUCTION

Filter by Model

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Part Models

Product Lifecycle

PCN

Oct 3, 2022

- 22_0207

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AD9542 Data Sheet Specification Revision

AD9542BCPZ

PRODUCTION

AD9542BCPZ-REEL7

PRODUCTION

Dec 13, 2018

- 18_0199

arrow down

AD9542 Data Sheet Specification Changes

AD9542BCPZ

PRODUCTION

AD9542BCPZ-REEL7

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-AD9542

AD9542 Evaluation Board

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EVAL-AD9542

AD9542 Evaluation Board

AD9542 Evaluation Board

Features and Benefits

  • Simple power connection using 6V wall adapter and on-board LDO voltage regulators.
  • 10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default).
  • 4 configurable reference inputs, selectable between a single ended to differential reference input SMA connector.
  • 1 ac-coupled single-ended input SMA connector for system clock.
  • Pin programmable, power on ready configurability.
  • Status LEDs.
  • USB connection to PC.
  • Microsoft Windows-based evaluation software with simple graphical user interface via an ACE plug-in module

Product Detail

The AD9542 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9542 dual digital PLL, synchronizer, and jitter cleaner. The AD9542 provides high-precision, multi-output clock generator functions, along with two on-chip jitter cleaning digital PLL cores. PLL0 and PLL1 are optimized for high performance synchronous clocking applications such as Synchronous Ethernet, OTN, and next generation wireless baseband protocols. The PLLs are fully configurable via serial port control as well as configurable via an external EEPROM for power on ready configurations.


The AD9542 can output up to 5 differential (or 10 single-ended) clock signals, plus two single-ended clocks driven by a mix of two high performance digital PLLs. 10 total outputs and 4 reference inputs are accessible on the evaluation board.


The output differential transmission line pairs use 50Ω single ended characteristic impedance and are connected to standard edge launch SMA connectors. The AD9542/PCBZ has a fully configurable power supply to allow the user to evaluate the AD9542 while being powered directly by a step down switching regulator or external LDOs. The AD9542 evaluation board uses RoHS-compliant FR-4 material. For convenience, detailed information from the AD9542 Datasheet has been included here. Use this user guide in conjunction with the datasheet that has been provided by ADI.

Tools & Simulations

Tools & Simulations 1

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