Features and Benefits
Product DetailsThe AD9522-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.
The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.
The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.
Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.
The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.
The AD9522 is specified for operation over the standard industrial range of −40°C to +85°C.
The AD9520-5 is an equivalent part to the AD9522-5 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.
1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family.
- Low jitter, low phase noise clock distribution
- Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
- Broadband infrastructures
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9522-x (hereafter referred to as AD9522) is a very low noise PLL clock synthesizer featuring an integrated VCO, clock dividers, and up to 24 outputs. The AD9522 features automatic holdover and a flexible reference input circuit allowing for very smooth reference clock switching. The AD9522 family also features the necessary provisions for an external VCXO.
The AD9522 evaluation board is a compact, easy to use platform for evaluating all features of the AD9522.
Features & Benefits
- Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- 5 ac-coupled differential LVDS SMA connectors
- 7 LVDS differential headers for additional outputs
- SMA connectors for
2 reference inputs
Charge pump output
Clock distribution input
- USB connection to PC
- Microsoft Windows-based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
Software & Systems Requirements
Tools & Simulations
AD9522-x IBIS Models
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.